Patents by Inventor Yi-Ju Chen

Yi-Ju Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11568121
    Abstract: A method of designing a circuit is provided. The method includes: providing a circuit; selecting a first NMOS fin field-effect transistor (FinFET) in the circuit; and replacing the first NMOS FinFET having a first fin number with a second NMOS FinFET having a second fin number and a third NMOS FinFET having a third fin number, wherein the sum of the second fin number and the third fin number is equal to the first fin number.
    Type: Grant
    Filed: April 9, 2021
    Date of Patent: January 31, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Tzu Chen, Hau-Tai Shieh, Che-Ju Yeh
  • Publication number: 20230008413
    Abstract: A method includes forming a fin protruding from a semiconductor substrate; forming a dummy gate stack over the fin, wherein forming the dummy gate stack includes depositing a layer of amorphous material over the fin; performing an anneal process on the layer of amorphous material, wherein the anneal process recrystallizes the layer of amorphous material into a layer of polycrystalline material, wherein the anneal process includes heating the layer of amorphous material for less than one millisecond; and patterning the layer of polycrystalline material; and forming an epitaxial source/drain region in the fin adjacent the dummy gate stack; and removing the dummy gate stack and replacing the dummy gate stack with a replacement gate stack.
    Type: Application
    Filed: February 16, 2022
    Publication date: January 12, 2023
    Inventors: Po-Kang Ho, Kuo-Ju Chen, Wei-Ting Chang, Wei-Fu Wang, Li-Ting Wang, Huicheng Chang, Yee-Chia Yeo, Yi-Chao Wang, Tsai-Yu Huang
  • Publication number: 20230007524
    Abstract: A method by a reduced capability wireless device includes receiving system information from a network node. The system information comprising information specific to the reduced capability wireless device. The reduced capability wireless device performs an operation using at least the information specific to the reduced capability wireless device received in the system information.
    Type: Application
    Filed: December 4, 2020
    Publication date: January 5, 2023
    Inventors: Yi-Pin Eric Wang, Xingqin Lin, Yutao Sui, Mohammad Mozaffari, Luca Faltrin, Yi-Ju Chen, Andreas Höglund
  • Publication number: 20230007603
    Abstract: A method of operating a wireless device in a wireless communication network. The method includes detecting first synchronization signaling of a first cell on first time and frequency resources. The first synchronization signaling comprises at least a first synchronization signal and a second synchronization signal. The method further includes detecting indication signaling on second time and frequency resources. The second time and frequency resources are derived based on the first time and frequency resources. The method further includes accessing the first cell if the indication signaling is detected on the second time and frequency resources. Accessing the first cell includes decoding a first system information message on a broadcast channel of the first cell. The first system information message indicates time and frequency resources of a first resource set. The disclosure also pertains to related devices and methods.
    Type: Application
    Filed: December 7, 2020
    Publication date: January 5, 2023
    Inventors: Yutao SUI, Yi-Pin Eric WANG, Johan LING, Andreas HÖGLUND, Olaf LIBERG, Yi-Ju CHEN, Mohammad MOZAFFARI
  • Patent number: 11545432
    Abstract: An exemplary semiconductor device includes a source feature and a drain feature disposed over a substrate. The semiconductor device further includes a source via electrically coupled to the source feature, and a drain via electrically coupled to the drain feature. The source via has a first size; the drain via has a second size; and the first size is greater than the second size. The semiconductor device may further include a first metal line electrically coupled to the source via and a second metal line electrically coupled to the drain via. The source via has a first dimension matching a dimension of the first metal line, and the drain via has a second dimension matching a dimension of the second metal line. The first metal line may be wider than the second metal line.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: January 3, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Kuo-Chiang Tsai, Yi-Ju Chen, Jyh-Huei Chen
  • Patent number: 11532627
    Abstract: A semiconductor device according to the present disclosure includes a first interconnect structure, a first transistor over the first interconnect structure, a second transistor over the first transistor, and a second interconnect structure over the second transistor. The first transistor includes first nanostructures and a first source region adjoining the first nanostructures. The second transistor includes second nanostructures and a second source region adjoining the second nanostructures. The first source region is coupled to a first power rail in the first interconnect structure, and the second source region is coupled to a second power rail in the second interconnect structure.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: December 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Bo Liao, Yu-Xuan Huang, Wei Ju Lee, Hou-Yu Chen, Chun-Fu Cheng
  • Patent number: 11520189
    Abstract: A display device includes a plurality of transparent voltage-dividing common electrodes and a plurality of pixel units. The transparent voltage-dividing common electrodes are electrically isolated from each other in a first direction. Each of the pixel units includes a first pixel electrode, a second pixel electrode, and a voltage-dividing switch. The first pixel electrode is configured to receive a data voltage. The second pixel electrode is configured to receive the data voltage. The voltage-dividing switch is configured to divide the data voltage on the second pixel electrode to one of the transparent voltage-dividing common electrodes.
    Type: Grant
    Filed: November 11, 2021
    Date of Patent: December 6, 2022
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Sheng-Ju Ho, Cheng-Han Tsao, Shang-Jie Wu, Yi-Jung Chen, Hung-Che Lin, Shun-Ling Hou, Nai-Wen Chang
  • Publication number: 20220376091
    Abstract: In a method of manufacturing a semiconductor device, a fin structure having a channel region protruding from an isolation insulating layer disposed over a semiconductor substrate is formed, a cleaning operation is performed, and an epitaxial semiconductor layer is formed over the channel region. The cleaning operation and the forming the epitaxial semiconductor layer are performed in a same chamber without breaking vacuum.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 24, 2022
    Inventors: Ya-Wen CHIU, Yi Che CHAN, Lun-Kuang TAN, Zheng-Yang PAN, Cheng-Po CHAU, Pin-Ju LIANG, Hung-Yao CHEN, De-Wei YU, Yi-Cheng LI
  • Publication number: 20220359393
    Abstract: A method includes receiving a semiconductor structure having a source contact feature electrically connected to a source feature and a drain contact feature electrically connected to a drain feature. The method includes etching to form a drain via trench over the drain contact feature and forming a drain via in the drain via trench. After forming the drain via, the method further includes etching to form a source via trench over the source contact feature and forming a source via in the source via trench. The drain via has a first dimension along a first direction, the source via has a second dimension along the first direction, and the second dimension is greater than the first dimension.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 10, 2022
    Inventors: Kuo-Chiang Tsai, Yi-Ju Chen, Jyh-Huei Chen
  • Publication number: 20220350375
    Abstract: A foldable electronic device is disclosed and includes a first body, a second body, a hinge mechanism, and a cover. The hinge mechanism includes a first rack plate disposed to the first body, a second rack plate disposed to the second body, a first gear shaft meshed with the first rack plate, and a second gear shaft meshed with the second rack plate and the first gear shaft. The cover is movably disposed on the hinge mechanism and covers the hinge mechanism. When the second body rotates relative to the first body, the second rack plate, the second gear shaft, the first gear shaft and the first rack plate rotate in sequence, the first rack plate and the second rack plate abut against the cover, so the cover is away from the hinge mechanism and separated from the first body and the second body.
    Type: Application
    Filed: February 9, 2022
    Publication date: November 3, 2022
    Applicant: ASUSTeK COMPUTER INC.
    Inventors: Po-Nien Chen, Yi-Ting Chen, Tsung-Ju Chiang
  • Publication number: 20220341724
    Abstract: A parallel optical scanning inspection device, comprising a light source unit, an interference unit, a beam splitting unit, an optical path adjustment unit, a plurality of scanning units and a receiving unit. The light source unit provides initial light to an interference unit. The interference unit divides the initial light into reference light and sampling light. The beam splitting unit splits the sampling light into a plurality of sampling light beams. The optical path adjustment unit adjusts the plurality of sampling light beams into scanning light beams with different optical paths. Each of the scanning units receives one of the scanning light beams. A sample is scanned by the scanning light beams such that each of the scanning units receives detection light reflected or scattered from different positions of the sample. The receiving unit receives and coheres the reference light and the detection light, respectively, to generate optical information.
    Type: Application
    Filed: November 8, 2021
    Publication date: October 27, 2022
    Inventors: WEN-JU CHEN, FENG-YU CHANG, YI-TING LIN
  • Publication number: 20220319861
    Abstract: A technique for semiconductor manufacturing is provided. The technique includes the operations as follows. A semiconductor structure having a first material is received. A plurality of first main etches are performed to the semiconductor structure for a plurality of first durations under the first etching chemistry. A plurality of pumping operations are performed for a plurality of pumping durations, each of the pumping operations being prior to each of the first main etches. Each of the first durations is in a range of from about 1 second to about 2.5 seconds.
    Type: Application
    Filed: June 24, 2022
    Publication date: October 6, 2022
    Inventors: HAN-YU LIN, LI-TE LIN, TZE-CHUNG LIN, FANG-WEI LEE, YI-LUN CHEN, JUNG-HAO CHANG, YI-CHEN LO, FO-JU LIN, KENICHI SANO, PINYEN LIN
  • Publication number: 20220284941
    Abstract: A memory device includes an array of memory cells and a plurality of peripheral circuits operably coupled to the memory array. A power control circuit may be configured to individually control an application of power to each of the plurality of peripheral circuits and the array of memory cells. Inserting a switch device across the different power domains to achieve the same sequential wake-up path for the peripheral circuits connected to different power domains reduces peak current.
    Type: Application
    Filed: May 25, 2022
    Publication date: September 8, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Ju Yeh, Hau-Tai Shieh, Yi-Tzu Chen
  • Publication number: 20220246522
    Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first vertical structure and a second vertical structure formed over the substrate, and a conductive rail structure between the first and second vertical structures. A top surface of the conductive rail structure can be substantially coplanar with top surfaces of the first and the second vertical structures.
    Type: Application
    Filed: April 18, 2022
    Publication date: August 4, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Bo Liao, Wei Ju LEE, Cheng-Ting CHUNG, Hou-Yu CHEN, Chun-Fu CHENG, Kuan-Lun CHENG
  • Patent number: 11373878
    Abstract: A technique for semiconductor manufacturing is provided. The technique includes the operations as follows. A semiconductor structure having a first material and a second material is revived. The first material has a first incubation time to a first etching chemistry. The second material has a second incubation time to the first etching chemistry. The first incubation time is shorter than the second incubation time. A first main etch to the semiconductor structure for a first duration by the first etching chemistry is performed. The first duration is greater than the first incubation time and shorter than the second incubation time.
    Type: Grant
    Filed: January 20, 2021
    Date of Patent: June 28, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Han-Yu Lin, Li-Te Lin, Tze-Chung Lin, Fang-Wei Lee, Yi-Lun Chen, Jung-Hao Chang, Yi-Chen Lo, Fo-Ju Lin, Kenichi Sano, Pinyen Lin
  • Publication number: 20220045073
    Abstract: The present application provides a method for preparing a memory device. The method includes: forming an active region in a substrate, wherein the active region has a linear top view shape; forming a gate structure on the substrate, wherein the gate structure has a linear portion intersected with a section of the active region away from end portions of the active region; forming a first insulating layer and a second insulating layer on the substrate, wherein the first insulating layer laterally surrounds the gate structure, and is covered by the second insulating layer; forming an opening penetrating through the first and second insulating layers and exposing a portion of the active region, wherein the opening is laterally spaced apart from the gate structure; and sequentially forming a dielectric layer and an electrode in the opening.
    Type: Application
    Filed: August 10, 2020
    Publication date: February 10, 2022
    Inventors: Chin-Ling HUANG, Jhen-Yu TSAI, Cheng-Han YANG, Yi-Ju CHEN
  • Patent number: 11244950
    Abstract: The present application provides a method for preparing a memory device. The method includes: forming an active region in a substrate, wherein the active region has a linear top view shape; forming a gate structure on the substrate, wherein the gate structure has a linear portion intersected with a section of the active region away from end portions of the active region; forming a first insulating layer and a second insulating layer on the substrate, wherein the first insulating layer laterally surrounds the gate structure, and is covered by the second insulating layer; forming an opening penetrating through the first and second insulating layers and exposing a portion of the active region, wherein the opening is laterally spaced apart from the gate structure; and sequentially forming a dielectric layer and an electrode in the opening.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: February 8, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chin-Ling Huang, Jhen-Yu Tsai, Cheng-Han Yang, Yi-Ju Chen
  • Patent number: 11241157
    Abstract: An upper gastrointestinal bleeding monitoring system includes a detection device and a signal processing device to determine bleeding condition of an upper gastrointestinal tract by using relation of time and intensity ratios of RGB three primary colors. The detecting device is placed to the upper gastrointestinal tract of a patient via his/her mouth or nasal passage and then stay the upper gastrointestinal tract for several days for detection of bleeding. The signal processing device may receive and display signal from the detection device to help medical professionals check if bleeding occurs in an upper gastrointestinal tract. Moreover, a procedure of determination of bleeding in an upper gastrointestinal tract with the upper gastrointestinal bleeding monitoring system is described.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: February 8, 2022
    Assignee: MediVisionTech Co., Ltd
    Inventors: Chiao-Hsiung Chuang, Chien-Cheng Chen, Yi-Ju Chen
  • Patent number: 11139203
    Abstract: A source/drain region is disposed in a substrate. A gate structure is disposed over the substrate. A gate spacer is disposed on a sidewall of the gate structure. The gate spacer and the gate structure have substantially similar heights. A via is disposed over and electrically coupled to: the source/drain region or the gate structure. A mask layer is disposed over the gate spacer. The mask layer has a greater dielectric constant than the gate spacer. A first side of the mask layer is disposed adjacent to the via. A dielectric layer is disposed on a second side of the mask layer, wherein the mask layer is disposed between the dielectric layer and the via.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: October 5, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Chiang Tsai, Ke-Jing Yu, Fu-Hsiang Su, Yi-Ju Chen, Jyh-Huei Chen
  • Publication number: 20210280742
    Abstract: A light-emitting element is provided, including a semiconductor structure, a reflective structure, first and second insulating structures, a conductive structure, and first and second pads. The reflective structure is disposed on the semiconductor structure. The first insulating structure includes first and second protrusions covering first and second portions respectively, and a first recession exposes a third portion between the first and second portions. The conductive structure includes first and second conductive portion. The first conductive portion is disposed on the first protrusion to contact the semiconductor structure. The second conductive portion is disposed on the second protrusion to contact the third portion through the first recession. The first and second pads are respectively disposed on the first and second conductive portions. Each of the structures below the first and second pads are in flat-type bonding to enhance stress resistance.
    Type: Application
    Filed: September 26, 2020
    Publication date: September 9, 2021
    Inventors: Pei-Shiu TSAI, Yi-Ju CHEN, Nai-Wei HSU, Wei-Chang YU