Patents by Inventor Yi-Ju Chen
Yi-Ju Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230116600Abstract: A semiconductor wafer, a benchmark device embedded on a semiconductor wafer, and a method of operating a benchmark device embedded on a semiconductor wafer are provided. The semiconductor wafer includes a benchmark device disposed within a scribe line of the semiconductor wafer. The benchmark device includes a transistor, a diode, and a disconnecting switch electrically connected to the transistor and the diode. The disconnecting switch is configured to form a conductive path between the transistor and the diode at a first stage, and to electrically isolate the transistor from the diode at a second stage.Type: ApplicationFiled: October 13, 2021Publication date: April 13, 2023Inventors: YI-JU CHEN, JUI-HSIU JAO
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Publication number: 20230072551Abstract: Embodiments include methods for a wireless device configured for random access to a cell of a wireless network. Such methods include transmitting, to a network node during a random-access procedure in the cell, a first indication of at least one capability of the wireless device. Such methods also include communicating with the network node, in one or more subsequent messages of the random-access procedure, using a configuration corresponding to the at least one capability indicated by the first indication. Other embodiments include complementary methods for a network node configured to support random access by wireless devices, as well as wireless devices and network nodes configured to perform such methods.Type: ApplicationFiled: February 4, 2021Publication date: March 9, 2023Inventors: Yutao Sui, Andreas Höglund, Luca Feltrin, Johan Bergman, Yi-Pin Eric Wang, Mohammad Mozaffari, Yi-Ju Chen
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Patent number: 11594658Abstract: A light-emitting element is provided, including a semiconductor structure, a reflective structure, first insulating structures, a conductive structure, and first and second pads. The reflective structure is disposed on the semiconductor structure. The first insulating structure includes first and second insulating portions covering first and second portions respectively, and a gap exposes a third portion between the first and second portions. The conductive structure includes first and second conductive portion. The first conductive portion is disposed on the first insulating portion to contact the semiconductor structure. The second conductive portion is disposed on the second insulating portion to contact the third portion through the gap. The first and second pads are respectively disposed on the first and second conductive portions. Each of the structures below the first and second pads are in flat-type bonding to enhance stress resistance.Type: GrantFiled: September 26, 2020Date of Patent: February 28, 2023Assignee: Lextar Electronics CorporationInventors: Pei-Shiu Tsai, Yi-Ju Chen, Nai-Wei Hsu, Wei-Chang Yu
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Publication number: 20230007524Abstract: A method by a reduced capability wireless device includes receiving system information from a network node. The system information comprising information specific to the reduced capability wireless device. The reduced capability wireless device performs an operation using at least the information specific to the reduced capability wireless device received in the system information.Type: ApplicationFiled: December 4, 2020Publication date: January 5, 2023Inventors: Yi-Pin Eric Wang, Xingqin Lin, Yutao Sui, Mohammad Mozaffari, Luca Faltrin, Yi-Ju Chen, Andreas Höglund
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Publication number: 20230007603Abstract: A method of operating a wireless device in a wireless communication network. The method includes detecting first synchronization signaling of a first cell on first time and frequency resources. The first synchronization signaling comprises at least a first synchronization signal and a second synchronization signal. The method further includes detecting indication signaling on second time and frequency resources. The second time and frequency resources are derived based on the first time and frequency resources. The method further includes accessing the first cell if the indication signaling is detected on the second time and frequency resources. Accessing the first cell includes decoding a first system information message on a broadcast channel of the first cell. The first system information message indicates time and frequency resources of a first resource set. The disclosure also pertains to related devices and methods.Type: ApplicationFiled: December 7, 2020Publication date: January 5, 2023Inventors: Yutao SUI, Yi-Pin Eric WANG, Johan LING, Andreas HÖGLUND, Olaf LIBERG, Yi-Ju CHEN, Mohammad MOZAFFARI
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Patent number: 11545432Abstract: An exemplary semiconductor device includes a source feature and a drain feature disposed over a substrate. The semiconductor device further includes a source via electrically coupled to the source feature, and a drain via electrically coupled to the drain feature. The source via has a first size; the drain via has a second size; and the first size is greater than the second size. The semiconductor device may further include a first metal line electrically coupled to the source via and a second metal line electrically coupled to the drain via. The source via has a first dimension matching a dimension of the first metal line, and the drain via has a second dimension matching a dimension of the second metal line. The first metal line may be wider than the second metal line.Type: GrantFiled: October 29, 2020Date of Patent: January 3, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Kuo-Chiang Tsai, Yi-Ju Chen, Jyh-Huei Chen
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Publication number: 20220359393Abstract: A method includes receiving a semiconductor structure having a source contact feature electrically connected to a source feature and a drain contact feature electrically connected to a drain feature. The method includes etching to form a drain via trench over the drain contact feature and forming a drain via in the drain via trench. After forming the drain via, the method further includes etching to form a source via trench over the source contact feature and forming a source via in the source via trench. The drain via has a first dimension along a first direction, the source via has a second dimension along the first direction, and the second dimension is greater than the first dimension.Type: ApplicationFiled: July 26, 2022Publication date: November 10, 2022Inventors: Kuo-Chiang Tsai, Yi-Ju Chen, Jyh-Huei Chen
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Publication number: 20220045073Abstract: The present application provides a method for preparing a memory device. The method includes: forming an active region in a substrate, wherein the active region has a linear top view shape; forming a gate structure on the substrate, wherein the gate structure has a linear portion intersected with a section of the active region away from end portions of the active region; forming a first insulating layer and a second insulating layer on the substrate, wherein the first insulating layer laterally surrounds the gate structure, and is covered by the second insulating layer; forming an opening penetrating through the first and second insulating layers and exposing a portion of the active region, wherein the opening is laterally spaced apart from the gate structure; and sequentially forming a dielectric layer and an electrode in the opening.Type: ApplicationFiled: August 10, 2020Publication date: February 10, 2022Inventors: Chin-Ling HUANG, Jhen-Yu TSAI, Cheng-Han YANG, Yi-Ju CHEN
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Patent number: 11244950Abstract: The present application provides a method for preparing a memory device. The method includes: forming an active region in a substrate, wherein the active region has a linear top view shape; forming a gate structure on the substrate, wherein the gate structure has a linear portion intersected with a section of the active region away from end portions of the active region; forming a first insulating layer and a second insulating layer on the substrate, wherein the first insulating layer laterally surrounds the gate structure, and is covered by the second insulating layer; forming an opening penetrating through the first and second insulating layers and exposing a portion of the active region, wherein the opening is laterally spaced apart from the gate structure; and sequentially forming a dielectric layer and an electrode in the opening.Type: GrantFiled: August 10, 2020Date of Patent: February 8, 2022Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Chin-Ling Huang, Jhen-Yu Tsai, Cheng-Han Yang, Yi-Ju Chen
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Patent number: 11241157Abstract: An upper gastrointestinal bleeding monitoring system includes a detection device and a signal processing device to determine bleeding condition of an upper gastrointestinal tract by using relation of time and intensity ratios of RGB three primary colors. The detecting device is placed to the upper gastrointestinal tract of a patient via his/her mouth or nasal passage and then stay the upper gastrointestinal tract for several days for detection of bleeding. The signal processing device may receive and display signal from the detection device to help medical professionals check if bleeding occurs in an upper gastrointestinal tract. Moreover, a procedure of determination of bleeding in an upper gastrointestinal tract with the upper gastrointestinal bleeding monitoring system is described.Type: GrantFiled: June 19, 2017Date of Patent: February 8, 2022Assignee: MediVisionTech Co., LtdInventors: Chiao-Hsiung Chuang, Chien-Cheng Chen, Yi-Ju Chen
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Patent number: 11139203Abstract: A source/drain region is disposed in a substrate. A gate structure is disposed over the substrate. A gate spacer is disposed on a sidewall of the gate structure. The gate spacer and the gate structure have substantially similar heights. A via is disposed over and electrically coupled to: the source/drain region or the gate structure. A mask layer is disposed over the gate spacer. The mask layer has a greater dielectric constant than the gate spacer. A first side of the mask layer is disposed adjacent to the via. A dielectric layer is disposed on a second side of the mask layer, wherein the mask layer is disposed between the dielectric layer and the via.Type: GrantFiled: January 31, 2019Date of Patent: October 5, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-Chiang Tsai, Ke-Jing Yu, Fu-Hsiang Su, Yi-Ju Chen, Jyh-Huei Chen
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Publication number: 20210280742Abstract: A light-emitting element is provided, including a semiconductor structure, a reflective structure, first and second insulating structures, a conductive structure, and first and second pads. The reflective structure is disposed on the semiconductor structure. The first insulating structure includes first and second protrusions covering first and second portions respectively, and a first recession exposes a third portion between the first and second portions. The conductive structure includes first and second conductive portion. The first conductive portion is disposed on the first protrusion to contact the semiconductor structure. The second conductive portion is disposed on the second protrusion to contact the third portion through the first recession. The first and second pads are respectively disposed on the first and second conductive portions. Each of the structures below the first and second pads are in flat-type bonding to enhance stress resistance.Type: ApplicationFiled: September 26, 2020Publication date: September 9, 2021Inventors: Pei-Shiu TSAI, Yi-Ju CHEN, Nai-Wei HSU, Wei-Chang YU
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Publication number: 20210272901Abstract: An exemplary semiconductor device includes a source feature and a drain feature disposed over a substrate. The semiconductor device further includes a source via electrically coupled to the source feature, and a drain via electrically coupled to the drain feature. The source via has a first size; the drain via has a second size; and the first size is greater than the second size. The semiconductor device may further include a first metal line electrically coupled to the source via and a second metal line electrically coupled to the drain via. The source via has a first dimension matching a dimension of the first metal line, and the drain via has a second dimension matching a dimension of the second metal line. The first metal line may be wider than the second metal line.Type: ApplicationFiled: October 29, 2020Publication date: September 2, 2021Inventors: Kuo-Chiang Tsai, Yi-Ju Chen, Jyh-Huei Chen
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Publication number: 20210202734Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a conductive gate stack formed over a substrate. A gate dielectric layer covers opposite sidewalls and a bottom of the conductive gate stack. A first gate spacer layer and a second gate spacer layer respectively cover portions of the gate dielectric layer corresponding to the opposite sidewalls of the conductive gate stack. A source/drain contact structure is separated from the conductive gate stack by the gate dielectric layer and the first gate spacer layer. A first insulating capping feature covers the conductive gate stack and is separated from the second gate spacer layer by the gate dielectric layer, and a second insulating capping feature covers the source/drain contact structure. An upper surface of the second insulating capping feature is substantially level with an upper surface of the first insulating capping feature.Type: ApplicationFiled: March 15, 2021Publication date: July 1, 2021Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Chiang TSAI, Fu-Hsiang SU, Yi-Ju CHEN, Jyh-Huei CHEN
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Patent number: 10982274Abstract: Disclosed are methods for nucleic acid amplification wherein nucleic acid templates, beads, and amplification reaction solution are emulsified and the nucleic acid templates are amplified to provide clonal copies of the nucleic acid templates attached to the beads. Also disclosed are kits and apparatuses for performing the methods of the invention.Type: GrantFiled: January 16, 2019Date of Patent: April 20, 2021Assignee: Roche Molecular Systems, Inc.Inventors: Jan Berka, Yi-Ju Chen, John H. Leamon, Steven Lefkowitz, Kenton L. Lohman, Vinod B. Makhijani, Jonathan M. Rothberg, Gary J. Sarkis, Maithreyan Srinivasan, Michael P. Weiner
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Patent number: 10950729Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate stack formed over a semiconductor substrate, a source/drain contact structure adjacent to the gate stack, and a gate spacer formed between the gate stack and the source/drain contact structure. The semiconductor device structure also includes a first insulating capping feature covering an upper surface of the gate stack, a second insulating capping feature covering an upper surface of the source/drain contact structure, and an insulating layer covering the upper surfaces of the first insulating capping feature and the second insulating capping feature. The second insulating capping feature includes a material that is different from a material of the first insulating capping feature. The semiconductor device structure also includes a via structure passing through the insulating layer and the first insulating capping feature and electrically connected to the gate stack.Type: GrantFiled: October 26, 2018Date of Patent: March 16, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuo-Chiang Tsai, Fu-Hsiang Su, Yi-Ju Chen, Jyh-Huei Chen
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Patent number: 10666438Abstract: A memory storage device is fabricated using a semiconductor fabrication process. Often times, manufacturing variations and/or misalignment tolerances present within the semiconductor fabrication process can cause the memory storage device to differ from other memory storage devices similarly designed and fabricated by the semiconductor fabrication process. For example, uncontrollable random physical processes in the semiconductor fabrication process can cause small differences, such as differences in doping concentrations, oxide thicknesses, channel lengths, structural widths, and/or parasitics to provide some examples, between these memory storage devices. These small differences can cause bitlines within the memory storage device to be physically unique with no two bitlines being identical. As a result, the uncontrollable random physical processes in the semiconductor fabrication process can cause electronic data read from the memory storage device to propagate along the bitlines at different rates.Type: GrantFiled: October 15, 2018Date of Patent: May 26, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jui-Che Tsai, Cheng Hung Lee, Shih-Lien Linus Lu, Yi-Ju Chen
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Publication number: 20200135912Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate stack formed over a semiconductor substrate, a source/drain contact structure adjacent to the gate stack, and a gate spacer formed between the gate stack and the source/drain contact structure. The semiconductor device structure also includes a first insulating capping feature covering an upper surface of the gate stack, a second insulating capping feature covering an upper surface of the source/drain contact structure, and an insulating layer covering the upper surfaces of the first insulating capping feature and the second insulating capping feature. The second insulating capping feature includes a material that is different from a material of the first insulating capping feature. The semiconductor device structure also includes a via structure passing through the insulating layer and the first insulating capping feature and electrically connected to the gate stack.Type: ApplicationFiled: October 26, 2018Publication date: April 30, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuo-Chiang TSAI, Fu-Hsiang SU, Yi-Ju CHEN, Jyh-Huei CHEN
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Publication number: 20200126857Abstract: A source/drain region is disposed in a substrate. A gate structure is disposed over the substrate. A gate spacer is disposed on a sidewall of the gate structure. The gate spacer and the gate structure have substantially similar heights. A via is disposed over and electrically coupled to: the source/drain region or the gate structure. A mask layer is disposed over the gate spacer. The mask layer has a greater dielectric constant than the gate spacer. A first side of the mask layer is disposed adjacent to the via. A dielectric layer is disposed on a second side of the mask layer, wherein the mask layer is disposed between the dielectric layer and the via.Type: ApplicationFiled: January 31, 2019Publication date: April 23, 2020Inventors: Kuo-Chiang Tsai, Ke-Jing Yu, Fu-Hsiang Su, Yi-Ju Chen, Jyh-Huei Chen
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Publication number: 20200020364Abstract: A memory storage device is fabricated using a semiconductor fabrication process. Often times, manufacturing variations and/or misalignment tolerances present within the semiconductor fabrication process can cause the memory storage device to differ from other memory storage devices similarly designed and fabricated by the semiconductor fabrication process. For example, uncontrollable random physical processes in the semiconductor fabrication process can cause small differences, such as differences in doping concentrations, oxide thicknesses, channel lengths, structural widths, and/or parasitics to provide some examples, between these memory storage devices. These small differences can cause bitlines within the memory storage device to be physically unique with no two bitlines being identical. As a result, the uncontrollable random physical processes in the semiconductor fabrication process can cause electronic data read from the memory storage device to propagate along the bitlines at different rates.Type: ApplicationFiled: October 15, 2018Publication date: January 16, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jui-Che TSAI, Cheng Hung LEE, Shih-Lien Linus LU, Yi-Ju CHEN