Patents by Inventor Yi-Nien Su
Yi-Nien Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9881794Abstract: In some embodiments, a method of a semiconductor process includes conformally forming a spacer layer over a plurality of mandrels that are disposed over a mask layer, portions of the spacer layer disposed over opposing sidewalls of adjacent ones of the plurality of mandrels defining trenches therebetween, filling the trenches with a dummy material, and removing first portions of the dummy material in the trenches, thereby forming a plurality of openings in the dummy material. The method further includes filling the plurality of openings with a first material, removing a remaining portion of the dummy material in the trenches, and removing the plurality of mandrels after the removing the dummy material.Type: GrantFiled: November 29, 2016Date of Patent: January 30, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Yi-Nien Su
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Patent number: 9530728Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes forming an etch stop layer over a workpiece. The etch stop layer has an etch selectivity to a material layer of the workpiece of greater than about 4 to about 30. The method includes forming an insulating material layer over the etch stop layer, and patterning the insulating material layer using the etch stop layer as an etch stop.Type: GrantFiled: September 4, 2015Date of Patent: December 27, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Su-Jen Sung, Yi-Nien Su
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Publication number: 20160358816Abstract: One or more techniques or systems for forming a semiconductor structure having a gap are provided herein. In some embodiments, a gap is formed between a first etch stop layer (ESL) and an ESL seal region. For example, the gap is formed by removing a portion of a low-k (LK) dielectric region above an oxide region and removing the oxide region. In some embodiments, the oxide region below the LK dielectric region facilitates removal of the LK dielectric region, at least because the oxide region enhances a bottom etch rate of a bottom of the LK dielectric region such that the bottom etch rate is similar to a wall etch rate of a wall of the LK dielectric region.Type: ApplicationFiled: August 22, 2016Publication date: December 8, 2016Inventors: Yi-Nien Su, Hsiang-Wei Lin
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Patent number: 9425091Abstract: One or more techniques or systems for forming a semiconductor structure having a gap are provided herein. In some embodiments, a gap is formed between a first etch stop layer (ESL) and an ESL seal region. For example, the gap is formed by removing a portion of a low-k (LK) dielectric region above an oxide region and removing the oxide region. In some embodiments, the oxide region below the LK dielectric region facilitates removal of the LK dielectric region, at least because the oxide region enhances a bottom etch rate of a bottom of the LK dielectric region such that the bottom etch rate is similar to a wall etch rate of a wall of the LK dielectric region.Type: GrantFiled: July 13, 2015Date of Patent: August 23, 2016Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yi-Nien Su, Hsiang-Wei Lin
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Patent number: 9355894Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower conductive feature in a lower low-k (LK) dielectric layer; a first etch stop layer (ESL) over the lower conductive feature, wherein the first ESL comprises a metal compound; an upper LK dielectric layer over the first ESL; and an upper conductive feature in the upper LK dielectric layer, wherein the upper conductive feature extends through the first ESL and connected to the lower conductive feature. The interconnect structure may further include a second ESL between the upper LK dielectric layer and the first ESL, or between the first ESL and the lower conductive feature, wherein the second ESL comprises a silicon compound.Type: GrantFiled: May 6, 2015Date of Patent: May 31, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Su-Jen Sung, Yi-Nien Su
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Publication number: 20150380352Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes forming an etch stop layer over a workpiece. The etch stop layer has an etch selectivity to a material layer of the workpiece of greater than about 4 to about 30. The method includes forming an insulating material layer over the etch stop layer, and patterning the insulating material layer using the etch stop layer as an etch stop.Type: ApplicationFiled: September 4, 2015Publication date: December 31, 2015Inventors: Su-Jen Sung, Yi-Nien Su
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Publication number: 20150318206Abstract: One or more techniques or systems for forming a semiconductor structure having a gap are provided herein. In some embodiments, a gap is formed between a first etch stop layer (ESL) and an ESL seal region. For example, the gap is formed by removing a portion of a low-k (LK) dielectric region above an oxide region and removing the oxide region. In some embodiments, the oxide region below the LK dielectric region facilitates removal of the LK dielectric region, at least because the oxide region enhances a bottom etch rate of a bottom of the LK dielectric region such that the bottom etch rate is similar to a wall etch rate of a wall of the LK dielectric region.Type: ApplicationFiled: July 13, 2015Publication date: November 5, 2015Inventors: Yi-Nien Su, Hsiang-Wei Lin
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Patent number: 9129965Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes forming an etch stop layer over a workpiece. The etch stop layer has an etch selectivity to a material layer of the workpiece of greater than about 4 to about 30. The method includes forming an insulating material layer over the etch stop layer, and patterning the insulating material layer using the etch stop layer as an etch stop.Type: GrantFiled: May 8, 2013Date of Patent: September 8, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Su-Jen Sung, Yi-Nien Su
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Publication number: 20150235894Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower conductive feature in a lower low-k (LK) dielectric layer; a first etch stop layer (ESL) over the lower conductive feature, wherein the first ESL comprises a metal compound; an upper LK dielectric layer over the first ESL; and an upper conductive feature in the upper LK dielectric layer, wherein the upper conductive feature extends through the first ESL and connected to the lower conductive feature. The interconnect structure may further include a second ESL between the upper LK dielectric layer and the first ESL, or between the first ESL and the lower conductive feature, wherein the second ESL comprises a silicon compound.Type: ApplicationFiled: May 6, 2015Publication date: August 20, 2015Inventors: Su-Jen Sung, Yi-Nien Su
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Patent number: 9082770Abstract: One or more techniques or systems for forming a damascene gap structure are provided herein. In some embodiments, a gap is formed between a first etch stop layer (ESL) and an ESL seal region. For example, the gap is formed by removing a portion of a low-k (LK) dielectric region above an oxide region and removing the oxide region. In some embodiments, the oxide region below the LK dielectric region facilitates removal of the LK dielectric region, at least because the oxide region enhances a bottom etch rate of a bottom of the LK dielectric region such that the bottom etch rate is similar to a wall etch rate of a wall of the LK dielectric region. In this manner, a damascene gap structure associated with a cleaner gap is provided, for example.Type: GrantFiled: October 24, 2012Date of Patent: July 14, 2015Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yi-Nien Su, Hsiang-Wei Lin
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Patent number: 9041216Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower conductive feature in a lower low-k (LK) dielectric layer; a first etch stop layer (ESL) over the lower conductive feature, wherein the first ESL comprises a metal compound; an upper LK dielectric layer over the first ESL; and an upper conductive feature in the upper LK dielectric layer, wherein the upper conductive feature extends through the first ESL and connected to the lower conductive feature. The interconnect structure may further include a second ESL between the upper LK dielectric layer and the first ESL, or between the first ESL and the lower conductive feature, wherein the second ESL comprises a silicon compound.Type: GrantFiled: June 19, 2013Date of Patent: May 26, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Su-Jen Sung, Yi-Nien Su
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Publication number: 20150137265Abstract: A fin field effect transistor and method of forming the same. The fin field effect transistor includes a semiconductor substrate having a fin structure and between two trenches with top portions and bottom portions. The fin field effect transistor further includes shallow trench isolations formed in the bottom portions of the trenches and a gate electrode over the fin structure and the shallow trench isolation, wherein the gate electrode is substantially perpendicular to the fin structure. The fin field effect transistor further includes a gate dielectric layer along sidewalls of the fin structure and source/drain electrode formed in the fin structure.Type: ApplicationFiled: December 24, 2014Publication date: May 21, 2015Inventors: Ju-Wang HSU, Chih-Yuan TING, Tang-Xuan ZHONG, Yi-Nien SU, Jang-Shiang TSAI
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Patent number: 8927353Abstract: A fin field effect transistor and method of forming the same. The fin field effect transistor includes a semiconductor substrate having a fin structure and between two trenches with top portions and bottom portions. The fin field effect transistor further includes shallow trench isolations formed in the bottom portions of the trenches and a gate electrode over the fin structure and the shallow trench isolation, wherein the gate electrode is substantially perpendicular to the fin structure. The fin field effect transistor further includes a gate dielectric layer along sidewalls of the fin structure and source/drain electrode formed in the fin structure.Type: GrantFiled: May 7, 2007Date of Patent: January 6, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ju-Wang Hsu, Chih-Yuan Ting, Tang-Xuan Zhong, Yi-Nien Su, Jang-Shiang Tsai
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Publication number: 20140264880Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a lower conductive feature in a lower low-k (LK) dielectric layer; a first etch stop layer (ESL) over the lower conductive feature, wherein the first ESL comprises a metal compound; an upper LK dielectric layer over the first ESL; and an upper conductive feature in the upper LK dielectric layer, wherein the upper conductive feature extends through the first ESL and connected to the lower conductive feature. The interconnect structure may further include a second ESL between the upper LK dielectric layer and the first ESL, or between the first ESL and the lower conductive feature, wherein the second ESL comprises a silicon compound.Type: ApplicationFiled: June 19, 2013Publication date: September 18, 2014Inventors: Su-Jen Sung, Yi-Nien Su
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Publication number: 20140272135Abstract: In deposition devices, a precursor is directed at a substrate within a deposition chamber, and a block plate comprising a set of block plate apertures adjusts the direction and volume of the outflowing precursor. However, arrangements of block plate apertures that are suitable for some deposition scenarios (such as one type of precursor) are unsuitable for other deposition scenarios, resulting in precursor deposition that is undesirably thick, thin, or inconsistent. A set of block plate masks positioned over respective zones of the block plate are adjustable to align a set of masking apertures with respect to the block plate apertures, such as by operating a block plate motor to rotate a ring-shaped block plate mask over a cylindrical zone of the block plate. This configuration enables adjustable exposure of the block plate apertures to control the adjusted outflow of precursor through the block plate.Type: ApplicationFiled: March 12, 2013Publication date: September 18, 2014Inventors: Chih-Chiang Chang, Yi-Nien Su, Su-Jen Sung, Chao-Chun Wang, Hsiang-Wei Lin
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Publication number: 20140264895Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes forming an etch stop layer over a workpiece. The etch stop layer has an etch selectivity to a material layer of the workpiece of greater than about 4 to about 30. The method includes forming an insulating material layer over the etch stop layer, and patterning the insulating material layer using the etch stop layer as an etch stop.Type: ApplicationFiled: May 8, 2013Publication date: September 18, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Su-Jen Sung, Yi-Nien Su
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Publication number: 20140110845Abstract: One or more techniques or systems for forming a damascene gap structure are provided herein. In some embodiments, a gap is formed between a first etch stop layer (ESL) and an ESL seal region. For example, the gap is formed by removing a portion of a low-k (LK) dielectric region above an oxide region and removing the oxide region. In some embodiments, the oxide region below the LK dielectric region facilitates removal of the LK dielectric region, at least because the oxide region enhances a bottom etch rate of a bottom of the LK dielectric region such that the bottom etch rate is similar to a wall etch rate of a wall of the LK dielectric region. In this manner, a damascene gap structure associated with a cleaner gap is provided, for example.Type: ApplicationFiled: October 24, 2012Publication date: April 24, 2014Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yi-Nien Su, Hsiang-Wel Lin
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Patent number: 8415799Abstract: A semiconductor device. A diffusion barrier layer overlies a substrate. An adhesion promoting layer overlies the diffusion barrier layer. A first dielectric layer between the diffusion barrier layer and the adhesion promoting layer comprises at least one via opening through the diffusion barrier layer and the adhesion promoting layer. A second dielectric layer overlies the adhesion promoting layer, comprising a trench opening above the via opening. A metal interconnect fills the via and trench openings.Type: GrantFiled: June 30, 2005Date of Patent: April 9, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Nien Su, Jyu-Horng Shieh, Hun-Jan Tao
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Patent number: 7875547Abstract: Methods and structures for forming a contact hole structure are disclosed. These methods first form a substantially silicon-free material layer over a substrate. A material layer is formed over the substantially silicon-free material layer. A contact hole is formed within the substantially silicon-free material layer and the material layer without substantially damaging the substrate. In addition, a conductive layer is formed in the contact hole so as to form a contact structure.Type: GrantFiled: January 12, 2005Date of Patent: January 25, 2011Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ju-Wang Hsu, Jyu-Horng Shieh, Yi-Nien Su, Peng-Fu Hsu, Hun-Jan Tao
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Patent number: 7598176Abstract: A plasma processing operation uses a gas mixture of N2 and H2 to both remove a photoresist film and treat a low-k dielectric material. The plasma processing operation prevents degradation of the low-k material by forming a protective layer on the low-k dielectric material. Carbon from the photoresist layer is activated and caused to complex with the low-k dielectric, maintaining a suitably high carbon content and a suitably low dielectric constant. The plasma processing operation uses a gas mixture with H2 constituting at least 10%, by volume, of the gas mixture.Type: GrantFiled: September 23, 2004Date of Patent: October 6, 2009Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.Inventors: Jang-Shiang Tsai, Yi-Nien Su, Chung-Chi Ko, Jyu-Horng Shieh, Peng-Fu Hsu, Hun-Jan Tao