Patents by Inventor Yi-Ruei JHAN
Yi-Ruei JHAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240112959Abstract: A method of fabricating a device includes forming a dummy gate over a plurality of fins. Thereafter, a first portion of the dummy gate is removed to form a first trench that exposes a first hybrid fin and a first part of a second hybrid fin. The method further includes filling the first trench with a dielectric material disposed over the first hybrid fin and over the first part of the second hybrid fin. Thereafter, a second portion of the dummy gate is removed to form a second trench and the second trench is filled with a metal layer. The method further includes etching-back the metal layer, where a first plane defined by a first top surface of the metal layer is disposed beneath a second plane defined by a second top surface of a second part of the second hybrid fin after the etching-back the metal layer.Type: ApplicationFiled: December 1, 2023Publication date: April 4, 2024Inventors: Kuan-Ting PAN, Zhi-Chang LIN, Yi-Ruei JHAN, Chi-Hao WANG, Huan-Chieh SU, Shi Ning JU, Kuo-Cheng CHIANG
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Patent number: 11908685Abstract: A method includes forming a gate spacer on sidewalls of a dummy gate structure disposed over a semiconductor substrate; performing a first implantation process to the gate spacer, wherein the first implantation process includes bombarding an upper portion of the gate spacer with silicon atoms; after performing the first implantation process, performing a second implantation process to the upper portion of the gate spacer, where the second implantation process includes bombarding the upper portion of the gate spacer with carbon atoms; and after performing the second implantation process, replacing the dummy gate structure with a high-k metal gate structure, wherein the replacing includes forming an interlayer dielectric (ILD) layer.Type: GrantFiled: March 15, 2021Date of Patent: February 20, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Ruei Jhan, Han-Yu Lin, Li-Te Lin, Pinyen Lin
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Publication number: 20240055479Abstract: A method for manufacturing a semiconductor structure is provided. The method includes forming a fin structure protruding from a substrate, wherein the fin structure includes first semiconductor material layers and second semiconductor material layers alternately stacked. The method includes forming a dummy gate structure across the fin structure. The method includes forming a gate spacer on the sidewall of the dummy gate structure. The method includes removing the dummy gate structure to expose the fin structure. The method includes partially removing the second semiconductor material layers to form concave portions on sidewalls of the second semiconductor material layers. The method includes forming dielectric spacers in the concave portions. The method includes removing the first semiconductor material layers to form gaps. The method includes forming a gate structure in the gaps to wrap around the second semiconductor material layers and the dielectric spacers.Type: ApplicationFiled: August 12, 2022Publication date: February 15, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuan-Ting PAN, Kuo-Cheng CHIANG, Shi-Ning JU, Yi-Ruei JHAN, Wei-Ting WANG, Chih-Hao WANG
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Publication number: 20230420532Abstract: A method of manufacturing an integrated circuit device is provided. The method includes forming a semiconductor fin over a semiconductor substrate; forming an isolation structure surrounding the semiconductor fin; etching a trench in the semiconductor fin; forming a dielectric fin in the trench; after forming the dielectric fin, recessing a top surface of the isolation structure, such that the dielectric fin and the semiconductor fin protrude from the recessed top surface of the isolation structure; and forming a first metal gate structure and a second metal gate structure over the dielectric fin and the semiconductor fin, respectively.Type: ApplicationFiled: June 27, 2022Publication date: December 28, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi-Ruei JHAN, Kuan-Ting PAN, Wei Ting WANG, Shi Ning JU, Kuo-Cheng CHIANG, Chih-Hao WANG
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Patent number: 11854908Abstract: A method of fabricating a device includes forming a dummy gate over a plurality of fins. Thereafter, a first portion of the dummy gate is removed to form a first trench that exposes a first hybrid fin and a first part of a second hybrid fin. The method further includes filling the first trench with a dielectric material disposed over the first hybrid fin and over the first part of the second hybrid fin. Thereafter, a second portion of the dummy gate is removed to form a second trench and the second trench is filled with a metal layer. The method further includes etching-back the metal layer, where a first plane defined by a first top surface of the metal layer is disposed beneath a second plane defined by a second top surface of a second part of the second hybrid fin after the etching-back the metal layer.Type: GrantFiled: May 9, 2022Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuan-Ting Pan, Huan-Chieh Su, Zhi-Chang Lin, Shi Ning Ju, Yi-Ruei Jhan, Kuo-Cheng Chiang, Chih-Hao Wang
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Publication number: 20230411499Abstract: A semiconductor structure includes a plurality of fin structures extending along a first direction, a plurality of gate structure segments positioned along a line extending in a second direction, the second direction being orthogonal to the first direction, wherein the gate structure segments are separated by dummy fin structures. The semiconductor structure further includes a conductive layer disposed over both the gate structure segments and the dummy fin structures to electrically connect at least some of the gate structure segments, and a cut feature aligned with one of the dummy fin structures and positioned to electrically isolate gate structure segments on both sides of the one of the dummy fin structures.Type: ApplicationFiled: July 28, 2023Publication date: December 21, 2023Inventors: Kuan-Ting Pan, Huan-Chieh Su, Jia-Chuan You, Shi Ning Ju, Kuo-Cheng Chiang, Yi-Ruei Jhan, Li-Yang Chuang, Chih-Hao Wang
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Publication number: 20230402506Abstract: Provided are a semiconductor device and a method of forming the same. The semiconductor device includes a semiconductor device. The semiconductor device includes a substrate including a plurality of fins, a plurality of semiconductor nanosheets stacked on the plurality of fins, a plurality of gate stacks wrapping the plurality of semiconductor nanosheets, an isolation structure around the plurality of fins, and a separator structure on the isolation structure to separate the plurality of gate stacks from each other. The separator structure includes a body and a cap on the body. The cap includes a first portion and a second portion. Sidewalls and bottom of the second portion is wrapped by the first portion.Type: ApplicationFiled: May 29, 2022Publication date: December 14, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Ruei Jhan, Kuan-Ting Pan, Yu-Wei Lu, Shi-Ning Ju, Kuo-Cheng Chiang, Chih-Hao Wang
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Publication number: 20230387227Abstract: A first interconnect structure (e.g., a gate interconnect) of a butted contact (BCT) is etched and filled. The first interconnect structure is then etched back such that a portion of the first interconnect structure is removed, then a second interconnect structure and the remaining portion of the first interconnect structure are filled. In this way, the height of the remaining portion of the first interconnect structure that is to be filled is closer to the height of the second interconnect structure when the second interconnect structure is filled relative to fully filling the second interconnect structure and fully filling the first interconnect structure in a single deposition operation. This reduces the likelihood that filling the second interconnect structure will close the first interconnect structure before the first interconnect structure can be fully filled, which may otherwise result in the formation of a void in the first interconnect structure.Type: ApplicationFiled: August 10, 2023Publication date: November 30, 2023Inventors: Te-Chih HSIUNG, I-Hung LI, Yi-Ruei JHAN, Yuan-Tien TU
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Publication number: 20230387117Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate having a base, a first fin, and a second fin over the base. The method includes forming a first nanostructure stack and a second nanostructure stack over the first fin and the second fin respectively. The method includes forming an isolation layer over the base. The method includes forming an isolation structure between the first fin and the second fin and between the first nanostructure stack and the second nanostructure stack. The isolation structure has an air gap. The method includes partially removing the isolation layer. The method includes forming a gate stack over the first nanostructure stack, the second nanostructure stack, the isolation structure, and the isolation layer.Type: ApplicationFiled: May 27, 2022Publication date: November 30, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Ruei JHAN, Kuo-Cheng CHIANG, Chih-Hao WANG
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Publication number: 20230369327Abstract: In a method of manufacturing a semiconductor device, a fin structure including a stacked layer of first semiconductor layers and second semiconductor layers is formed, an isolation insulating layer is formed so that the stacked layer are exposed from the isolation insulating layer, a sacrificial cladding layer is formed over at least sidewalls of the exposed stacked layer, a sacrificial gate electrode is formed over the exposed stacked layer, an interlayer dielectric layer is formed, the sacrificial gate electrode is partially recessed to leave a pillar of the remaining sacrificial gate electrode, the sacrificial cladding layer and the first semiconductor layers are removed, a gate dielectric layer wrapping around the second semiconductor layer and a gate electrode over the gate dielectric layer are formed, the pillar is removed, and one or more dielectric layers are formed in a gate space from which the pillar is removed.Type: ApplicationFiled: July 12, 2022Publication date: November 16, 2023Inventors: Kuan-Ting PAN, Kuo-Cheng CHIANG, Shi Ning JU, Yi-Ruei JHAN, Wei Ting WANG, Chih-Hao WANG
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Publication number: 20230369463Abstract: The present disclosure provides a method for using a hard mask layer on a top surface of fin structures to form a fin-top mask layer. The fin-top mask layer can function as an etch stop for subsequent processes. Using the fin-top hard mask layer allows a thinner conformal dielectric layer to be used to protect semiconductor fins during the subsequent process, such as during etching of sacrificial gate electrode layer. Using a thinner conformal dielectric layer can reduce the pitch of fins, particularly for input/output devices.Type: ApplicationFiled: July 27, 2023Publication date: November 16, 2023Inventors: YI-RUEI JHAN, KUAN-TING PAN, KUO-CHENG CHIANG, KUAN-LUN CHENG, CHIH-HAO WANG
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Patent number: 11799019Abstract: A semiconductor structure includes a plurality of fin structures extending along a first direction, a plurality of gate structure segments positioned along a line extending in a second direction, the second direction being orthogonal to the first direction, wherein the gate structure segments are separated by dummy fin structures. The semiconductor structure further includes a conductive layer disposed over both the gate structure segments and the dummy fin structures to electrically connect at least some of the gate structure segments, and a cut feature aligned with one of the dummy fin structures and positioned to electrically isolate gate structure segments on both sides of the one of the dummy fin structures.Type: GrantFiled: November 6, 2020Date of Patent: October 24, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuan-Ting Pan, Huan-Chieh Su, Jia-Chuan You, Shi Ning Ju, Kuo-Cheng Chiang, Yi-Ruei Jhan, Li-Yang Chuang, Chih-Hao Wang
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Publication number: 20230290859Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a plurality of first nanostructures stacked over a substrate in a vertical direction. The semiconductor device structure includes a first gate structure surrounding the first nanostructures. The semiconductor device structure also includes a first gate spacer layer formed adjacent to the first gate structure. A topmost first nanostructure has a first portion directly below the gate spacer layer and a second portion directly below the first gate structure, and the first portion has a first height along the vertical direction, the second portion has a second height along the vertical direction, and the first height is greater than the second height.Type: ApplicationFiled: March 9, 2022Publication date: September 14, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Ruei JHAN, Kuo-Cheng CHIANG, Chih-Hao WANG
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Patent number: 11757021Abstract: The present disclosure provide a method for using a hard mask layer on a top surface of fin structures to form a fin-top mask layer. The fin-top mask layer can function as an etch stop for subsequent processes. Using the fin-top hard mask layer allows a thinner conformal dielectric layer to be used to protect semiconductor fins during the subsequent process, such as during etching of sacrificial gate electrode layer. Using a thinner conformal dielectric layer can reduce the pitch of fins, particularly for input/output devices.Type: GrantFiled: August 18, 2020Date of Patent: September 12, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Ruei Jhan, Kuan-Ting Pan, Kuo-Cheng Chiang, Kuan-Lun Cheng, Chih-Hao Wang
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Publication number: 20230282520Abstract: A semiconductor device includes a substrate, a semiconductor fin protruding from the substrate, an isolation layer disposed above the substrate, a dielectric fin with a bottom portion embedded in the isolation layer, and a gate structure over top and sidewall surfaces of the semiconductor fin and the dielectric fin. The semiconductor fin has a first sidewall and a second sidewall facing away from the first sidewall. The isolation layer includes a first portion disposed on the first sidewall of the semiconductor fin and a second portion disposed on the second sidewall of the semiconductor fin. A top portion of the dielectric fin includes an air pocket with a top opening sealed by the gate structure.Type: ApplicationFiled: May 8, 2023Publication date: September 7, 2023Inventors: Han-Yu Lin, Yi-Ruei Jhan, Fang-Wei Lee, Tze-Chung Lin, Chao-Hsien Huang, Li-Te Lin, Pinyen Lin, Akira Mineji
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Publication number: 20230223305Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor stack, a second semiconductor stack, a first gate structure, and a second gate structure. The semiconductor substrate comprising a first device region and a second device region. The first semiconductor stack is located on the semiconductor substrate over the first device region, and has first channels. The second semiconductor stack is located on the semiconductor substrate over the second device region, and has second channels. A total number of the first channels is greater than a total number of the second channels. The first gate structure encloses the first semiconductor stack. The second gate structure encloses the second semiconductor stack.Type: ApplicationFiled: March 8, 2023Publication date: July 13, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuan-Ting Pan, Chih-Hao Wang, Kuo-Cheng Chiang, Yi-Bo Liao, Yi-Ruei Jhan
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Publication number: 20230178555Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a semiconductor fin including a first surface, a second surface opposite the first surface, a third surface connecting the first surface and the second surface, and a fourth surface opposite the third surface. The semiconductor device structure further includes a gate electrode layer disposed adjacent the first, third, and fourth surfaces of the semiconductor fin, a first source/drain epitaxial feature in contact with the semiconductor fin, and a first inner spacer disposed between the first source/drain epitaxial feature and the gate electrode layer. The first inner spacer is in contact with the first source/drain epitaxial feature, and the first inner spacer comprises a first material. The semiconductor device structure further includes a first spacer in contact with the first inner spacer, and the first spacer comprises a second material different from the first material.Type: ApplicationFiled: January 30, 2023Publication date: June 8, 2023Inventors: Kuan-Ting PAN, Kuo-Cheng CHIANG, Shi-Ning JU, Yi-Ruei JHAN, Kuan-Lun CHENG, Chih-Hao WANG
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Patent number: 11646234Abstract: A semiconductor device includes a semiconductor substrate, a semiconductor fin protruding from the semiconductor substrate, and an isolation layer disposed above the semiconductor substrate. The isolation layer includes a first portion disposed on a first sidewall of the semiconductor fin and a second portion disposed on a second sidewall of the semiconductor fin. Top surfaces of the first and second portions of the isolation layer are leveled. The first portion of the isolation layer includes an air pocket. The semiconductor device also includes a dielectric fin with a bottom portion embedded in the second portion of the isolation layer.Type: GrantFiled: June 29, 2021Date of Patent: May 9, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Han-Yu Lin, Yi-Ruei Jhan, Fang-Wei Lee, Tze-Chung Lin, Chao-Hsien Huang, Li-Te Lin, Pinyen Lin, Akira Mineji
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Publication number: 20230124914Abstract: Embodiments of the present disclosure provide a method of forming sidewall spacers by filling a trench between a hybrid fin and a semiconductor fin structure. The sidewall spacer includes two fin sidewall spacer portions connected by a gate sidewall spacer portion. The fin sidewall spacer portion has a substantially uniform profile to provide uniform protection for vertically stacked channel layers and eliminate any gaps and leaks between inner spacers and sidewall spacers.Type: ApplicationFiled: December 19, 2022Publication date: April 20, 2023Inventors: Kuan-Ting Pan, Kuo-Cheng CHIANG, Shi Ning JU, Yi-Ruei Jhan, KUAN-LUN CHENG, CHIH-HAO WANG
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Patent number: 11621195Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor stack, a second semiconductor stack, a first gate structure, and a second gate structure. The semiconductor substrate comprising a first device region and a second device region. The first semiconductor stack is located on the semiconductor substrate over the first device region, and has first channels. The second semiconductor stack is located on the semiconductor substrate over the second device region, and has second channels. A total number of the first channels is greater than a total number of the second channels. The first gate structure encloses the first semiconductor stack. The second gate structure encloses the second semiconductor stack.Type: GrantFiled: April 23, 2020Date of Patent: April 4, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuan-Ting Pan, Chih-Hao Wang, Kuo-Cheng Chiang, Yi-Bo Liao, Yi-Ruei Jhan