Abstract: A device includes a substrate, a first semiconductor channel over the substrate, and a second semiconductor channel over the substrate laterally offset from the first semiconductor channel. A first gate structure and a second gate structure are over and laterally surround the first and second semiconductor channels, respectively. A first inactive fin is between the first gate structure and the second gate structure. A dielectric feature over the inactive fin includes multiple layers of dielectric material formed through alternating deposition and etching steps.

Abstract: A device includes a substrate, a first semiconductor fin over the substrate extending in a first lateral direction, a first vertical stack of semiconductor nanosheets over the substrate extending in the first lateral direction, and an inactive fin between the first semiconductor fin and the first vertical stack extending in the first lateral direction. A first gate structure surrounds and covers the first semiconductor fin, and extends in a second lateral direction substantially perpendicular to the first lateral direction. A second gate structure surrounds and covers the first vertical stack, and extends in the second lateral direction.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a substrate and first nanostructures and second nanostructures formed over the substrate. The semiconductor structure also includes a gate structure including a first portion wrapping around the first nanostructures and a second portion wrapping around the second nanostructures. The semiconductor structure also includes a dielectric feature sandwiched between the first portion and the second portion of the gate structure. In addition, the dielectric feature includes a bottom portion and a top portion over the bottom portion, and the top portion of the dielectric feature includes a shell layer and a core portion surrounded by the shell layer.

Abstract: A device includes a substrate, a first semiconductor channel over the substrate, a second semiconductor channel over the substrate and laterally offset from the first semiconductor channel, an isolation feature embedded in the substrate and laterally between the first and second semiconductor channels, a first liner layer laterally surrounding the isolation feature between the isolation feature and the first semiconductor channel, and a second liner layer laterally surrounding the first liner layer between the first liner layer and the first semiconductor channel.

Abstract: A first interconnect structure (e.g., a gate interconnect) of a butted contact (BCT) is etched and filled. The first interconnect structure is then etched back such that a portion of the first interconnect structure is removed, then a second interconnect structure and the remaining portion of the first interconnect structure are filled. In this way, the height of the remaining portion of the first interconnect structure that is to be filled is closer to the height of the second interconnect structure when the second interconnect structure is filled relative to fully filling the second interconnect structure and fully filling the first interconnect structure in a single deposition operation. This reduces the likelihood that filling the second interconnect structure will close the first interconnect structure before the first interconnect structure can be fully filled, which may otherwise result in the formation of a void in the first interconnect structure.

Abstract: A device includes a substrate, a first stack of semiconductor nanostructures vertically overlying the substrate, and a gate structure surrounding the semiconductor nanostructures and abutting an upper side and first and second lateral sides of the first stack. A first epitaxial region laterally abuts a third lateral side of the first stack, and a second epitaxial region laterally abuts a fourth lateral side of the first stack. A first inactive fin laterally abuts the first epitaxial region, and a second inactive fin laterally abuts the second epitaxial region and is physically separated from the first inactive fin by the gate structure.

Abstract: A device includes a substrate and a fin isolation structure between a first gate structure and a second gate structure. The first gate structure wraps around a first vertical stack of nanostructure channels overlying a first fin. The second gate structure wraps around a second vertical stack of nanostructure channels overlying a second fin. The fin isolation structure extends from an upper surface of the first gate structure to an upper surface of the substrate. A trench isolation structure is between the first fin and the fin isolation structure, and has different etch selectivity than the fin isolation structure.

Abstract: Gate isolation techniques disclosed herein form gate isolation fins to isolate metal gates of multigate devices from one another before forming the multigate devices, and in particular, before forming the metal gates of the multigate devices. An exemplary device includes a first multigate device having first source/drain features and a first metal gate that surrounds a first channel layer and a second multigate device having second source/drain features and a second metal gate that surrounds a second channel layer. A gate isolation fin, which separates the first metal gate and the second metal gate, includes a dielectric feature having a first dielectric layer having a first dielectric constant (e.g., a low-k dielectric core) and a second dielectric layer (e.g., a high-k dielectric shell) surrounding the first dielectric layer. The second dielectric layer has a second dielectric constant that is greater than the first dielectric constant.

Abstract: According to one example, a semiconductor structure includes a fin-shaped structure, a gate structure disposed over a region of the fin-shaped structure and having a sidewall including a lower portion and an upper portion above the lower portion, a first dielectric sidewall structure disposed along the lower portion of the sidewall, a second dielectric sidewall structure disposed along the upper portion of the sidewall and disposed on the first dielectric sidewall structure, and a source/drain feature disposed over a source/drain region of the fin-shaped structure and adjacent to the gate structure. The source/drain feature is separated from the gate structure by the first dielectric sidewall structure and the second dielectric sidewall structure. The first dielectric sidewall structure includes a different material than the second dielectric sidewall structure.

Abstract: A semiconductor fabrication apparatus includes a processing chamber for etching, a substrate stage integrated in the processing chamber and being configured to secure a semiconductor wafer, and a gas distribution plate integrated inside the processing chamber. The processing chamber includes a sidewall and a top surface. The semiconductor fabrication apparatus further includes a heating mechanism disposed on the sidewall of the processing chamber and is operable to perform a baking process to remove a by-product generated during the etching, and a reflective mirror configured inside the processing chamber to reflect thermal energy from the heating mechanism toward the semiconductor wafer, the reflective mirror being located on the top surface of the processing chamber. The gas distribution plate defines a portion of the top surface of the processing chamber. From a top view, a portion of the reflective mirror is disposed between the heating mechanism and the gas distribution plate.

Abstract: A semiconductor structure includes a plurality of fin structures extending along a first direction, a plurality of gate structure segments positioned along a line extending in a second direction, the second direction being orthogonal to the first direction, wherein the gate structure segments are separated by dummy fin structures. The semiconductor structure further includes a conductive layer disposed over both the gate structure segments and the dummy fin structures to electrically connect at least some of the gate structure segments, and a cut feature aligned with one of the dummy fin structures and positioned to electrically isolate gate structure segments on both sides of the one of the dummy fin structures.

Abstract: A first interconnect structure (e.g., a gate interconnect) of a butted contact (BCT) is etched and filled. The first interconnect structure is then etched back such that a portion of the first interconnect structure is removed, then a second interconnect structure and the remaining portion of the first interconnect structure are filled. In this way, the height of the remaining portion of the first interconnect structure that is to be filled is closer to the height of the second interconnect structure when the second interconnect structure is filled relative to fully filling the second interconnect structure and fully filling the first interconnect structure in a single deposition operation. This reduces the likelihood that filling the second interconnect structure will close the first interconnect structure before the first interconnect structure can be fully filled, which may otherwise result in the formation of a void in the first interconnect structure.

Abstract: Embodiments of the present disclosure provide a method of forming sidewall spacers by filling a trench between a hybrid fin and a semiconductor fin structure. The sidewall spacer includes two fin sidewall spacer portions connected by a gate sidewall spacer portion. The fin sidewall spacer portion has a substantially uniform profile to provide uniform protection for vertically stacked channel layers and eliminate any gaps and leaks between inner spacers and sidewall spacers.

Abstract: A method for fabricating semiconductor devices includes forming a stack structure protruding from a substrate and including a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked on top of one another. The method includes forming an isolation structure overlaying the substrate and a lower portion of the stack structure. The method includes implanting dopants into at least an upper portion of the isolation structure.

Abstract: A device includes a substrate and a fin isolation structure between a first gate structure and a second gate structure. The first gate structure wraps around a first vertical stack of nanostructure channels overlying a first fin. The second gate structure wraps around a second vertical stack of nanostructure channels overlying a second fin. The fin isolation structure extends from an upper surface of the first gate structure to an upper surface of the substrate. A trench isolation structure is between the first fin and the fin isolation structure, and has different etch selectivity than the fin isolation structure.

Abstract: According to one example, a method includes forming a first set of fin structures on a substrate, forming a sacrificial material between fin structures within the first set of fin structures, forming a dummy gate with a planar bottom surface over the fin structures and the sacrificial material, forming sidewall structures on the dummy gate, laterally etching the sacrificial material underneath the sidewall structures, depositing a lower sidewall structure where the sacrificial material was removed, removing the dummy gate, removing the sacrificial material, and forming a real gate over the fin structures.

Abstract: Gate isolation techniques disclosed herein form gate isolation fins to isolate metal gates of multigate devices from one another before forming the multigate devices, and in particular, before forming the metal gates of the multigate devices. An exemplary device includes a first multigate device having first source/drain features and a first metal gate that surrounds a first channel layer and a second multigate device having second source/drain features and a second metal gate that surrounds a second channel layer. A gate isolation fin, which separates the first metal gate and the second metal gate, includes a dielectric feature having a first dielectric layer having a first dielectric constant (e.g., a low-k dielectric core) and a second dielectric layer (e.g., a high-k dielectric shell) surrounding the first dielectric layer. The second dielectric layer has a second dielectric constant that is greater than the first dielectric constant.

Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor stack, a second semiconductor stack, a first gate structure, and a second gate structure. The semiconductor substrate comprising a first device region and a second device region. The first semiconductor stack is located on the semiconductor substrate over the first device region, and has first channels. The second semiconductor stack is located on the semiconductor substrate over the second device region, and has second channels. A total number of the first channels is greater than a total number of the second channels. The first gate structure encloses the first semiconductor stack. The second gate structure encloses the second semiconductor stack.

Abstract: The present disclosure provides a semiconductor fabrication apparatus. The semiconductor apparatus includes a processing chamber for etching; a substrate stage integrated in the processing chamber and being configured to secure a semiconductor wafer; a reflective mirror configured inside the processing chamber to reflect thermal energy from the heating mechanism toward the semiconductor wafer; and a heating mechanism embedded in the process chamber and is operable to perform a baking process to remove a by-product generated during the etching. The heating mechanism is integrated between the reflective mirror and a gas distribution plate of the processing chamber.

Abstract: A method for forming a nanosheet device is provided. The method includes epitaxially growing a conformal semiconductor layer from a first stack of semiconductor layers and a second stack of the semiconductor layers. Each of the first and second stack of semiconductor layers includes a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked on each other. A space between the first and second stacks of semiconductor layers is filled with a dielectric fin. The conformal semiconductor layer and the second semiconductor layers may be removed. A metal gate structure is formed over the first semiconductor layers and filling openings created by removal of the conformal semiconductor layer and the second semiconductor layer. A process may be performed on the metal gate structure to form an isolation between the portions of the metal gate structure being separated by a patterning process.