Patents by Inventor Yi-Shien Mor

Yi-Shien Mor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11004747
    Abstract: Integrated circuit devices having optimized fin critical dimension loading are disclosed herein. An exemplary integrated circuit device includes a core region that includes a first multi-fin structure and an input/output region that includes a second multi-fin structure. The first multi-fin structure has a first width and the second multi-fin structure has a second width. The first width is greater than the second width. In some implementations, the first multi-fin structure has a first fin spacing and the second multi-fin structure has a second fin spacing. The first fin spacing is less than the second fin spacing. In some implementations, a first adjacent fin pitch of the first multi-fin structure is greater than or equal to three times a minimum fin pitch and a second adjacent fin pitch of the second multi-fin structure is less than or equal to two times the minimum fin pitch.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: May 11, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia Ming Liang, Yi-Shien Mor, Huai-Hsien Chiu, Chi-Hsin Chang, Jin-Aun Ng, Yi-Juei Lee
  • Publication number: 20200381428
    Abstract: A semiconductor device includes a first fin field effect transistor (FinFET) and a contact bar (source/drain (S/D) contact layer). The first FinFET includes a first fin structure extending in a first direction, a first gate structure extending in a second direction crossing the first direction, and a first S/D structure. The contact bar is disposed over the first S/D structure and extends in the second direction crossing the first S/D structure in plan view. The contact bar includes a first portion disposed over the first S/D structure and a second portion. The second portion overlaps no fin structure and no S/D structure. A width of the second portion in the first direction is smaller than a width of the first portion in the first direction in plan view.
    Type: Application
    Filed: August 17, 2020
    Publication date: December 3, 2020
    Inventors: Chih-Hao CHANG, Wen-Huei GUO, Yi-Shien MOR
  • Publication number: 20200273754
    Abstract: Integrated circuit devices having optimized fin critical dimension loading are disclosed herein. An exemplary integrated circuit device includes a core region that includes a first multi-fin structure and an input/output region that includes a second multi-fin structure. The first multi-fin structure has a first width and the second multi-fin structure has a second width. The first width is greater than the second width. In some implementations, the first multi-fin structure has a first fin spacing and the second multi-fin structure has a second fin spacing. The first fin spacing is less than the second fin spacing. In some implementations, a first adjacent fin pitch of the first multi-fin structure is greater than or equal to three times a minimum fin pitch and a second adjacent fin pitch of the second multi-fin structure is less than or equal to two times the minimum fin pitch.
    Type: Application
    Filed: May 11, 2020
    Publication date: August 27, 2020
    Inventors: Chia Ming Liang, Yi-Shien Mor, Huai-Hsien Chiu, Chi-Hsin Chang, Jin-Aun Ng, Yi-Juei Lee
  • Patent number: 10748896
    Abstract: A semiconductor device includes a first fin field effect transistor (FinFET) and a contact bar (source/drain (S/D) contact layer). The first FinFET includes a first fin structure extending in a first direction, a first gate structure extending in a second direction crossing the first direction, and a first S/D structure. The contact bar is disposed over the first S/D structure and extends in the second direction crossing the first S/D structure in plan view. The contact bar includes a first portion disposed over the first S/D structure and a second portion. The second portion overlaps no fin structure and no S/D structure. A width of the second portion in the first direction is smaller than a width of the first portion in the first direction in plan view.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: August 18, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Hao Chang, Yi-Shien Mor, Wen-Huei Guo
  • Patent number: 10692769
    Abstract: Integrated circuit devices having optimized fin critical dimension loading are disclosed herein. An exemplary integrated circuit device includes a core region that includes a first multi-fin structure and an input/output region that includes a second multi-fin structure. The first multi-fin structure has a first width and the second multi-fin structure has a second width. The first width is greater than the second width. In some implementations, the first multi-fin structure has a first fin spacing and the second multi-fin structure has a second fin spacing. The first fin spacing is less than the second fin spacing. In some implementations, a first adjacent fin pitch of the first multi-fin structure is greater than or equal to three times a minimum fin pitch and a second adjacent fin pitch of the second multi-fin structure is less than or equal to two times the minimum fin pitch.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: June 23, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chia Ming Liang, Yi-Shien Mor, Huai-Hsien Chiu, Chi-Hsin Chang, Jin-Aun Ng, Yi-Juei Lee
  • Patent number: 10651090
    Abstract: Integrated circuit devices having optimized fin critical dimension loading are disclosed herein. An exemplary integrated circuit device includes a core region that includes a first multi-fin structure and an input/output region that includes a second multi-fin structure. The first multi-fin structure has a first width and the second multi-fin structure has a second width. The first width is greater than the second width. In some implementations, the first multi-fin structure has a first fin spacing and the second multi-fin structure has a second fin spacing. The first fin spacing is less than the second fin spacing. In some implementations, a first adjacent fin pitch of the first multi-fin structure is greater than or equal to three times a minimum fin pitch and a second adjacent fin pitch of the second multi-fin structure is less than or equal to two times the minimum fin pitch.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: May 12, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chia Ming Liang, Yi-Shien Mor, Huai-Hsien Chiu, Chi-Hsin Chang, Jin-Aun Ng, Yi-Juei Lee
  • Patent number: 10529862
    Abstract: A semiconductor device includes a substrate, an epitaxial channel structure and a gate structure. The epitaxial channel structure is located above the substrate. The epitaxial channel structure has a bottom and a top. The bottom is between the substrate and the top, and the bottom has a width less than that of the top.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: January 7, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Ming Liang, Huai-Hsien Chiu, Yi-Shien Mor
  • Patent number: 10366989
    Abstract: A semiconductor device includes a first fin field effect transistor (FinFET) and a contact bar (source/drain (S/D) contact layer). The first FinFET includes a first fin structure extending in a first direction, a first gate structure extending in a second direction crossing the first direction, and a first S/D structure. The contact bar is disposed over the first S/D structure and extends in the second direction crossing the first S/D structure in plan view. The contact bar includes a first portion disposed over the first S/D structure and a second portion. The second portion overlaps no fin structure and no S/D structure. A width of the second portion in the first direction is smaller than a width of the first portion in the first direction in plan view.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: July 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Hao Chang, Wen-Huei Guo, Yi-Shien Mor
  • Publication number: 20190189614
    Abstract: A method includes forming a first fin on a semiconductor substrate, forming an isolation dielectric material over the first fin, and planarizing the isolation dielectric material. A top surface of the first fin is covered by the isolation dielectric material after planarizing the isolation dielectric material. The method further includes etching back the isolation dielectric material until the first fin protrudes from the isolation dielectric material.
    Type: Application
    Filed: February 11, 2019
    Publication date: June 20, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Juei LEE, Chia-Ming LIANG, Chi-Hsin CHANG, Jin-Aun NG, Yi-Shien MOR, Huai-Hsien CHIU
  • Publication number: 20190067112
    Abstract: Integrated circuit devices having optimized fin critical dimension loading are disclosed herein. An exemplary integrated circuit device includes a core region that includes a first multi-fin structure and an input/output region that includes a second multi-fin structure. The first multi-fin structure has a first width and the second multi-fin structure has a second width. The first width is greater than the second width. In some implementations, the first multi-fin structure has a first fin spacing and the second multi-fin structure has a second fin spacing. The first fin spacing is less than the second fin spacing. In some implementations, a first adjacent fin pitch of the first multi-fin structure is greater than or equal to three times a minimum fin pitch and a second adjacent fin pitch of the second multi-fin structure is less than or equal to two times the minimum fin pitch.
    Type: Application
    Filed: October 31, 2017
    Publication date: February 28, 2019
    Inventors: Chia Ming Liang, Yi-Shien Mor, Huai-Hsien Chiu, Chi-Hsin Chang, Jin-Aun Ng, Yi-Juei Lee
  • Patent number: 10204905
    Abstract: A semiconductor structure includes a substrate, a first gate structure, and a second gate structure. The substrate has a plurality of first fins and a plurality of second fins, wherein a first pitch between two adjacent first fins is greater than a second pitch between two adjacent second fins. The first gate structure crosses over the first fins. The second gate structure crosses over the second fins, wherein the second gate structure includes an upper portion having two first sidewalls substantially parallel to each other and a lower portion tapers toward the substrate.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: February 12, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Juei Lee, Chia-Ming Liang, Chi-Hsin Chang, Jin-Aun Ng, Yi-Shien Mor, Huai-Hsien Chiu
  • Publication number: 20180337177
    Abstract: A semiconductor device includes a first fin field effect transistor (FinFET) and a contact bar (source/drain (S/D) contact layer). The first FinFET includes a first fin structure extending in a first direction, a first gate structure extending in a second direction crossing the first direction, and a first S/D structure. The contact bar is disposed over the first S/D structure and extends in the second direction crossing the first S/D structure in plan view. The contact bar includes a first portion disposed over the first S/D structure and a second portion. The second portion overlaps no fin structure and no S/D structure. A width of the second portion in the first direction is smaller than a width of the first portion in the first direction in plan view.
    Type: Application
    Filed: July 30, 2018
    Publication date: November 22, 2018
    Inventors: Chih-Hao CHANG, Yi-Shien MOR, Wen-Huei GUO
  • Publication number: 20180308842
    Abstract: A semiconductor structure includes a substrate, a first gate structure, and a second gate structure. The substrate has a plurality of first fins and a plurality of second fins, wherein a first pitch between two adjacent first fins is greater than a second pitch between two adjacent second fins. The first gate structure crosses over the first fins. The second gate structure crosses over the second fins, wherein the second gate structure includes an upper portion having two first sidewalls substantially parallel to each other and a lower portion tapers toward the substrate.
    Type: Application
    Filed: June 23, 2017
    Publication date: October 25, 2018
    Inventors: Yi-Juei LEE, Chia-Ming LIANG, Chi-Hsin CHANG, Jin-Aun NG, Yi-Shien MOR, Huai-Hsien CHIU
  • Publication number: 20180247937
    Abstract: A semiconductor device includes a semiconductor substrate, an isolation structure in the semiconductor substrate for isolating a first active region and a second active region, a first device formed in the first active region, and a second device formed in the second active region. The first device has a first gate dielectric layer and a first gate electrode over the first gate dielectric layer. The first gate electrode includes at least one of Ta and C, and has a first work function for a first conductivity. The second device has a second gate dielectric layer and a second gate electrode over the second gate dielectric layer. The second gate electrode includes at least one of Ta, C, and Al, and has a second work function for a second conductivity. The second conductivity is different from the first conductivity.
    Type: Application
    Filed: April 25, 2018
    Publication date: August 30, 2018
    Inventors: Yih-Ann Lin, Ryan Chia-Jen Chen, Donald Y. Chao, Yi-Shien Mor, Kuo-Tai Huang
  • Publication number: 20180151739
    Abstract: A semiconductor device includes a substrate, an epitaxial channel structure and a gate structure. The epitaxial channel structure is located above the substrate. The epitaxial channel structure has a bottom and a top. The bottom is between the substrate and the top, and the bottom has a width less than that of the top.
    Type: Application
    Filed: January 20, 2017
    Publication date: May 31, 2018
    Inventors: Chia-Ming Liang, Huai-Hsien Chiu, Yi-Shien Mor
  • Patent number: 9960160
    Abstract: The present disclosure describes a semiconductor device. The device includes a semiconductor substrate, an isolation structure formed in the substrate for isolating a first active region and a second active region, a first transistor formed in the first active region, the first transistor having a high-k gate dielectric layer and a metal gate with a first work function formed over the high-k gate dielectric layer, and a second transistor formed in the second active region, the second transistor having the high-k gate dielectric layer and a metal gate with a second work function formed over the high-k gate dielectric layer. The metal gates are formed from at least a single metal layer having the first work function and the second work function.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: May 1, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yih-Ann Lin, Ryan Chia-Jen Chen, Donald Y. Chao, Yi-Shien Mor, Kuo-Tai Huang
  • Publication number: 20170229454
    Abstract: A semiconductor device includes a first fin field effect transistor (FinFET) and a contact bar (source/drain (S/D) contact layer). The first FinFET includes a first fin structure extending in a first direction, a first gate structure extending in a second direction crossing the first direction, and a first S/D structure. The contact bar is disposed over the first S/D structure and extends in the second direction crossing the first S/D structure in plan view. The contact bar includes a first portion disposed over the first S/D structure and a second portion. The second portion overlaps no fin structure and no S/D structure. A width of the second portion in the first direction is smaller than a width of the first portion in the first direction in plan view.
    Type: Application
    Filed: October 21, 2016
    Publication date: August 10, 2017
    Inventors: Chih-Hao CHANG, Wen-Huei GUO, Yi-Shien MOR
  • Patent number: 9601388
    Abstract: A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first region and a second region, forming a first dielectric layer over the semiconductor substrate, forming a first metal layer over the first dielectric layer, the first metal layer having a first work function, removing at least a portion of the first metal layer in the second region, and thereafter, forming a semiconductor layer over the first metal layer in the first region and over the at least partially removed first metal layer in the second region. The method further includes removing the semiconductor layer and forming a second metal layer on the first metal layer in the first region and on the at least partially removed first metal layer in the second region, the second metal layer having a second work function that is different than the first work function.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: March 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ryan Chia-Jen Chen, Jr-Jung Lin, Chien-Hao Chen, Yi-Hsing Chen, Kuo-Tai Huang, Yih-Ann Lin, Yi-Shien Mor
  • Patent number: 9466696
    Abstract: A device includes a semiconductor fin, a gate dielectric on sidewalls of the semiconductor fin, a gate electrode over the gate dielectric, and isolation regions. The isolation regions include a first portion on a side of the semiconductor fin, wherein the first portion is underlying and aligned to a portion of the gate electrode. The semiconductor fin is over a first top surface of the first portion of the isolation regions. The isolation regions further include second portions on opposite sides of the portion of the gate electrode. The second top surfaces of the second portions of the isolation regions are higher than the first top surface of the isolation regions.
    Type: Grant
    Filed: January 24, 2012
    Date of Patent: October 11, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Shien Mor, Hsiao-Chu Chen, Mu-Chi Chiang
  • Patent number: 9466528
    Abstract: A method of making a structure includes forming a first supporting member over a substrate, the first supporting member comprising a first material and having a first width defined along a reference plane. The method further includes forming a second supporting member over the substrate, the second supporting member having a second width defined along the reference plane, and the first supporting member and the second supporting member being separated by a gap region. The first width is at least 10 times the second width, and a gap width of the gap region being from 5 to 30 times the second width.
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: October 11, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Chu Liu, Yi-Shien Mor, Kuei-Shun Chen, Yu Lun Liu, Han-Hsun Chang, Shiao-Chian Yeh