Patents by Inventor Yi-Tang LIN

Yi-Tang LIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9773809
    Abstract: A multilayer semiconductor device structure comprising a first buried oxide and a first semiconductor device layer fabricated above the first buried oxide is provided. The first semiconductor device layer comprises a patterned top surface. The patterned surface comprises insulator material and conductor material. The surface density of the insulator material is greater than 40 percent. The multilayer semiconductor device structure further comprises a second buried oxide bonded to the patterned surface of the first semiconductor device layer and a second semiconductor device layer fabricated above the second buried oxide.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: September 26, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LIMITED
    Inventors: Yi-Tang Lin, Chun-Hsiung Tsai, Clement Hsingjen Wann
  • Publication number: 20170271503
    Abstract: A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.
    Type: Application
    Filed: June 5, 2017
    Publication date: September 21, 2017
    Inventors: Shao-Ming YU, Chang-Yun CHANG, Chih-Hao CHANG, Hsin-Chih CHEN, Kai-Tai CHANG, Ming-Feng SHIEH, Kuei-Liang LU, Yi-Tang LIN
  • Patent number: 9704880
    Abstract: A semiconductor structure having multiple semiconductor-device layers is provided. The semiconductor structure comprises a first buried oxide and a first semiconductor device layer fabricated above the first buried oxide. The first semiconductor device layer comprises a patterned top surface. A blanket layer comprising insulator material is fabricated over the patterned surface. The semiconductor structure further comprises a second buried oxide bonded to the blanket layer and a second semiconductor device layer fabricated above the second buried oxide.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: July 11, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yi-Tang Lin, Chun-Hsiung Tsai, Clement Hsingjen Wann
  • Patent number: 9673328
    Abstract: A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: June 6, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shao-Ming Yu, Chang-Yun Chang, Chih-Hao Chang, Hsin-Chih Chen, Kai-Tai Chang, Ming-Feng Shieh, Kuei-Liang Lu, Yi-Tang Lin
  • Patent number: 9666490
    Abstract: Methods for fabricating multiple inverter structures in a multi-layer semiconductor structure are provided. A first device layer is formed on a substrate. The first device layer comprises one or more first inverter structures including a first input terminal and a first output terminal. A second device layer is formed on the first device layer. The second device layer comprises one or more second inverter structures including a second input terminal and a second output terminal. One or more inter-layer connection structures are formed. The one or more inter-layer connection structures are disposed to electrically connect the first input terminal to the second output terminal and electrically connect the first output terminal to the second input terminal.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: May 30, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: I-Fan Lin, Yi-Tang Lin, Cheng-Hung Yeh, Hsien-Hsin Sean Lee, Chou-Kun Lin
  • Patent number: 9646872
    Abstract: A multilayer semiconductor device structure having different circuit functions on different semiconductor device layers is provided. The semiconductor structure comprises a first semiconductor device layer fabricated on a bulk substrate. The first semiconductor device layer comprises a first semiconductor device for performing a first circuit function. The first semiconductor device layer includes a patterned top surface of different materials. The semiconductor structure further comprises a second semiconductor device layer fabricated on a semiconductor-on-insulator (“SOI”) substrate. The second semiconductor device layer comprises a second semiconductor device for performing a second circuit function. The second circuit function is different from the first circuit function. A bonding surface coupled between the patterned top surface of the first semiconductor device layer and a bottom surface of the SOI substrate is included.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: May 9, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yi-Tang Lin, Chun-Hsiung Tsai, Clement Hsingjen Wann
  • Patent number: 9634001
    Abstract: A FinFET structure layout includes a semiconductor substrate comprising a plurality of FinFET active areas, and a plurality of fins within each FinFET active area of the plurality of FinFET active areas. The FinFET structure layout further includes a gate having a gate length parallel to the semiconductor substrate and perpendicular to length of the plurality of fins within each FinFET active area of the plurality of FinFET active areas. The FinFET structure layout further includes a plurality of metal features connecting a source region or a drain region of a portion of the plurality of FinFET active areas to a plurality of contacts. The plurality of metal features includes a plurality of metal lines parallel to a FinFET channel direction and a plurality of metal lines parallel to a FinFET channel width direction.
    Type: Grant
    Filed: July 28, 2014
    Date of Patent: April 25, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Clement Hsingjen Wann, Chih-Sheng Chang, Yi-Tang Lin, Ming-Feng Shieh, Ting-Chu Ko, Chung-Hsien Chen
  • Patent number: 9553025
    Abstract: A method of forming a fin field-effect transistor (FinFET) includes forming a plurality of fins on a substrate. The method further includes forming an oxide layer on the substrate, wherein a bottom portion of each fin of the plurality of fins is embedded in the oxide layer, and the bottom portion of each fin of the plurality of fins has substantially a same shape. The method further includes shaping at least one fin of the plurality of fins, wherein a top portion of the at least one fin has a different shape from a top portion of another fin of the plurality of fins.
    Type: Grant
    Filed: January 16, 2015
    Date of Patent: January 24, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Clement Hsingjen Wann, Ling-Yen Yeh, Chi-Yuan Shih, Yi-Tang Lin, Chih-Sheng Chang, Chi-Wen Liu
  • Publication number: 20170012045
    Abstract: A method includes providing a first substrate having first and second regions, fabricating over the first region of the first substrate a channel of a first transistor, providing a second substrate over the second region of the first substrate, fabricating over the second substrate a channel of a second transistor, and forming gates respectively and simultaneously over the channels of the first and second transistors.
    Type: Application
    Filed: September 26, 2016
    Publication date: January 12, 2017
    Inventors: YI-TANG LIN, Clement HSINGJEN WANN
  • Publication number: 20160379994
    Abstract: A multilayer semiconductor device structure comprising a first buried oxide and a first semiconductor device layer fabricated above the first buried oxide is provided. The first semiconductor device layer comprises a patterned top surface. The patterned surface comprises insulator material and conductor material. The surface density of the insulator material is greater than 40 percent. The multilayer semiconductor device structure further comprises a second buried oxide bonded to the patterned surface of the first semiconductor device layer and a second semiconductor device layer fabricated above the second buried oxide.
    Type: Application
    Filed: September 12, 2016
    Publication date: December 29, 2016
    Inventors: YI-TANG LIN, CHUN-HSIUNG TSAI, CLEMENT HSINGJEN WANN
  • Patent number: 9525049
    Abstract: A method of fabricating a Fin field effect transistor (FinFET) includes providing a substrate having a first fin and a second fin extending above a substrate top surface, wherein the first fin has a top surface and sidewalls and the second fin has a top surface and sidewalls. The method includes forming an insulation layer between the first and second fins. The method includes forming a first gate dielectric having a first thickness covering the top surface and sidewalls of the first fin using a plasma doping process. The method includes forming a second gate dielectric covering the top surface and sidewalls of the second fin having a second thickness less than the first thickness. The method includes forming a conductive gate strip traversing over both the first gate dielectric and the second gate dielectric.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: December 20, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Clement Hsingjen Wann, Ling-Yen Yeh, Chi-Yuan Shih, Yi-Tang Lin, Chih-Sheng Chang
  • Patent number: 9472550
    Abstract: A method includes growing a plurality of parallel mandrels on a surface of a semiconductor substrate, each mandrel having at least two laterally opposite sidewalls and a predetermined width. The method further includes forming a first type of spacers on the sidewalls of the mandrels, wherein the first type of spacers between two adjacent mandrels are separated by a gap. The predetermined mandrel width is adjusted to close the gap between the adjacent first type of spacers to form a second type of spacers. The mandrels are removed to form a first type of fins from the first type of spacers, and to form a second type of fins from spacers between two adjacent mandrels. The second type of fins are wider than the first type of fins.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: October 18, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Hsun Wang, Chih-Sheng Chang, Yi-Tang Lin
  • Patent number: 9472672
    Abstract: An embodiment fin field-effect transistor (FinFET) includes an inner fin, and outer fin spaced apart from the inner fin by a shallow trench isolation (STI) region, an isolation fin spaced apart from the outer fin by the STI region, the isolation fin including a body portion, an isolation oxide, and an etch stop layer, the etch stop layer interposed between the body portion and the isolation oxide and between the STI region and the isolation oxide, and a gate formed over the inner fin, the outer fin, and the isolation fin.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: October 18, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Tang Lin, Chih-Yu Hsu, Clement Hsingjen Wann, Chih-Sheng Chang
  • Patent number: 9461069
    Abstract: An aspect of the instant disclosure provides a multilayer device structure that comprises: a substrate defining a first device region and a second device region laterally offsetting each other; a first channel material layer disposed over the substrate in the first device region; a second channel material layer over the substrate in the second device region, wherein the second channel material layer is arranged at an elevation higher than the first channel material layer; and a first device and a second device respectively fabricated from the first and the second channel material layers, wherein the first device and the second device vertically offsetting each other and defining an offset region above the first device, thereby reducing parasitic interference there-between.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: October 4, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yi-Tang Lin, Clement Hsingjen Wann
  • Publication number: 20160284603
    Abstract: Systems and methods are provided for fabricating a semiconductor structure including an inverter chain. An example semiconductor structure includes a first device layer, a second device layer, and one or more inter-layer connection structures. The first device layer is formed on a substrate and includes one or more first inverter structures. The second device layer is formed on the first device layer and includes one or more second inverter structures. The one or more inter-layer connection structures are configured to electrically connect to the first inverter structures and the second inverter structures.
    Type: Application
    Filed: June 6, 2016
    Publication date: September 29, 2016
    Inventors: I-Fan Lin, YI-TANG LIN, CHENG-HUNG YEH, HSIEN-HSIN SEAN LEE, CHOU-KUN LIN
  • Patent number: 9443869
    Abstract: A multilayer semiconductor device structure comprising a first buried oxide and a first semiconductor device layer fabricated above the first buried oxide is provided. The first semiconductor device layer comprises a patterned top surface. The patterned surface comprises insulator material and conductor material. The surface density of the insulator material is greater than 40 percent. The multilayer semiconductor device structure further comprises a second buried oxide bonded to the patterned surface of the first semiconductor device layer and a second semiconductor device layer fabricated above the second buried oxide.
    Type: Grant
    Filed: November 5, 2013
    Date of Patent: September 13, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yi-Tang Lin, Chun-Hsiung Tsai, Clement Hsingjen Wann
  • Publication number: 20160247920
    Abstract: A method includes providing a plurality of semiconductor fins parallel to each other, and includes two edge fins and a center fin between the two edge fins. A middle portion of each of the two edge fins is etched, and the center fin is not etched. A gate dielectric is formed on a top surface and sidewalls of the center fin. A gate electrode is formed over the gate dielectric. The end portions of the two edge fins and end portions of the center fin are recessed. An epitaxy is performed to form an epitaxy region, wherein an epitaxy material grown from spaces left by the end portions of the two edge fins are merged with an epitaxy material grown from a space left by the end portions of the center fin to form the epitaxy region. A source/drain region is formed in the epitaxy region.
    Type: Application
    Filed: May 2, 2016
    Publication date: August 25, 2016
    Inventors: Chia-Cheng Ho, Tzu-Chiang Chen, Yi-Tang Lin, Chih-Sheng Chang
  • Publication number: 20160240675
    Abstract: A method includes forming an isolation feature in a semiconductor substrate; forming a first fin-like active region and a second fin-like active region in the semiconductor substrate and interposed by the isolation feature; forming a dummy gate stack on the isolation feature, wherein the dummy gate extends to the first fin-like active region from one side and to the second fin-like active region from another side.
    Type: Application
    Filed: April 25, 2016
    Publication date: August 18, 2016
    Inventors: Shao-Ming Yu, Chang-Yun Chang, Chih-Hao Chang, Hsin-Chih Chen, Kai-Tai Chang, Ming-Feng Shieh, Kuei-Liang Lu, Yi-Tang Lin
  • Patent number: 9379217
    Abstract: A method includes providing a plurality of semiconductor fins parallel to each other, and includes two edge fins and a center fin between the two edge fins. A middle portion of each of the two edge fins is etched, and the center fin is not etched. A gate dielectric is formed on a top surface and sidewalls of the center fin. A gate electrode is formed over the gate dielectric. The end portions of the two edge fins and end portions of the center fin are recessed. An epitaxy is performed to form an epitaxy region, wherein an epitaxy material grown from spaces left by the end portions of the two edge fins are merged with an epitaxy material grown from a space left by the end portions of the center fin to form the epitaxy region. A source/drain region is formed in the epitaxy region.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: June 28, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Cheng Ho, Tzu-Chiang Chen, Yi-Tang Lin, Chih-Sheng Chang
  • Patent number: 9373623
    Abstract: Systems and methods are provided for fabricating a semiconductor structure including an inverter chain. An example semiconductor structure includes a first device layer, a second device layer, and one or more inter-layer connection structures. The first device layer is formed on a substrate and includes one or more first inverter structures. The second device layer is formed on the first device layer and includes one or more second inverter structures. The one or more inter-layer connection structures are configured to electrically connect to the first inverter structures and the second inverter structures.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: June 21, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: I-Fan Lin, Yi-Tang Lin, Cheng-Hung Yeh, Hsien-Hsin Sean Lee, Chou-Kun Lin