Patents by Inventor Yi-Ting Liao

Yi-Ting Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230064635
    Abstract: In an exemplary aspect, the present disclosure is directed to a device. The device includes a semiconductor substrate, a stack of semiconductor layers over the semiconductor substrate, a gate structure over and between the stack of semiconductor layers, where the gate structure engages with the stack of semiconductor layers. Moreover, the device also includes a silicide layer extending along sidewall surfaces of the stack of semiconductor layers, and a source/drain feature on a sidewall surface of the silicide layer.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Inventors: Yu-Xuan Huang, Wang-Chun Huang, Yi-Bo Liao, Cheng-Ting Chung, Hou-Yu Chen, Kuan-Lun Cheng, Wei Ju Lee
  • Publication number: 20230048684
    Abstract: A MOS capacitor includes a substrate having a capacitor forming region thereon, an ion well having a first conductivity type in the substrate, a counter doping region having a second conductivity type in the ion well within the capacitor forming region, a capacitor dielectric layer on the ion well within the capacitor forming region, a gate electrode on the capacitor dielectric layer, a source doping region having the second conductivity type on a first side of the gate electrode within the capacitor forming region, and a drain doping region having the second conductivity type on a second side of the gate electrode within the capacitor forming region.
    Type: Application
    Filed: October 31, 2022
    Publication date: February 16, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Jian-Li Lin, Wei-Da Lin, Cheng-Guo Chen, Ta-Kang Lo, Yi-Chuan Chen, Huan-Chi Ma, Chien-Wen Yu, Kuan-Ting Lu, Kuo-Yu Liao
  • Publication number: 20230052295
    Abstract: A device includes a substrate, a gate structure, a capping layer, a source/drain region, a source/drain contact, and an air spacer. The gate structure wraps around at least one vertical stack of nanostructure channels over the substrate. The capping layer is on the gate structure. The source/drain region abuts the gate structure. The source/drain contact is on the source/drain region. The air spacer is between the capping layer and the source/drain contact.
    Type: Application
    Filed: January 20, 2022
    Publication date: February 16, 2023
    Inventors: Yi-Bo LIAO, Yu-Xuan HUANG, Cheng-Ting CHUNG, Hou-Yu CHEN
  • Patent number: 11555981
    Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a stopping assembly. The fixed assembly has a main axis. The movable assembly is configured to connect an optical element, and the movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The stopping assembly is configured to limit the movement of the movable assembly relative to the fixed assembly within a range of motion.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: January 17, 2023
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Liang-Ting Ho, Chen-Er Hsu, Yi-Liang Chan, Fu-Lai Tseng, Fu-Yuan Wu, Chen-Chi Kuo, Ying-Jen Wang, Wei-Han Hsia, Yi-Hsin Tseng, Wen-Chang Lin, Chun-Chia Liao, Shou-Jen Liu, Chao-Chun Chang, Yi-Chieh Lin, Shang-Yu Hsu, Yu-Huai Liao, Shih-Wei Hung, Sin-Hong Lin, Kun-Shih Lin, Yu-Cheng Lin, Wen-Yen Huang, Wei-Jhe Shen, Chih-Shiang Wu, Sin-Jhong Song, Che-Hsiang Chiu, Sheng-Chang Lin
  • Patent number: 11532715
    Abstract: A semiconductor device includes a first source/drain region and a second source/drain region disposed on opposite sides of a plurality of conductive layers. A dielectric layer overlies the first source/drain region, the second source/drain region, and the plurality of conductive layers. An electrical contact extends through the dielectric layer and the first source/drain region, where a first surface of the electrical contact is a surface of the electrical contact that is closest to the substrate, a first surface of the plurality of conductive layers is a surface of the plurality of conductive layers that is closest to the substrate, and the first surface of the electrical contact is closer to the substrate than the first surface of the plurality of conductive layers.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: December 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ching-Wei Tsai, Yi-Bo Liao, Cheng-Ting Chung, Yu-Xuan Huang, Kuan-Lun Cheng
  • Publication number: 20220367660
    Abstract: The present disclosure describes a method for forming metallization layers that include a ruthenium metal liner and a cobalt metal fill. The method includes depositing a first dielectric on a substrate having a gate structure and source/drain (S/D) structures, forming an opening in the first dielectric to expose the S/D structures, and depositing a ruthenium metal on bottom and sidewall surfaces of the opening. The method further includes depositing a cobalt metal on the ruthenium metal to fill the opening, reflowing the cobalt metal, and planarizing the cobalt and ruthenium metals to form S/D conductive structures with a top surface coplanar with a top surface of the first dielectric.
    Type: Application
    Filed: May 14, 2021
    Publication date: November 17, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shuen-Shin Liang, Chih-Chien Chi, Chien-Shun Liao, Keng-Chu Lin, Kai-Ting Huang, Sung-Li Wang, Yi-Ying Liu, Chia-Hung Chu, Hsu-Kai Chang, Cheng-Wei Chang
  • Patent number: 11500012
    Abstract: A semiconductor component burn-in test module includes a burn-in board and an external power transmission component. The burn-in board includes a plurality of burn-in seats, wherein a plurality of chips are disposed on the burn-in seats. The external power transmission component is arranged at opposite two sides of the burn-in board, where the external power transmission component includes a plurality of conductive members and a plurality of terminal seats. The burn-in board is provided with a plurality of wirings corresponding to the external power transmission component. As such, electric power can be conveyed to the plural burn-in seats of the burn-in board, through the plural terminal seats and the plural conductive strips. This decreases the length and the number of copper foil wirings in the burn-in boards for power transmission, so as to lower the cost of the burn-in boards.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: November 15, 2022
    Assignee: KING YUAN ELECTRONICS CO., LTD.
    Inventors: Chia-Hung Tsai, Kuo-Jung Wu, Hsing-Yueh Liang, Po-Wei Liao, Yi-Ting Wang
  • Publication number: 20220344398
    Abstract: A method of fabricating a solid-state image sensor, including steps of forming a second type doped semiconductor layer and a semiconductor material layer sequentially on a first type doped semiconductor substrate to constitute a photoelectric conversion portion, forming a multilayer structure on the semiconductor material layer, wherein a refractive index of the multilayer structure gradually decreases from a bottom layer to a top layer of the multilayer structure and is smaller than a refractive index of the semiconductor material layer, and performing a photolithography process to the multiplayer structure and the photoelectric conversion portion to form multiple micro pillars, wherein the micro pillars protrude from the semiconductor material layer and are isolated by recesses extending into the photoelectric conversion portion.
    Type: Application
    Filed: July 10, 2022
    Publication date: October 27, 2022
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Shih-Ping Lee, Yi-Ping Lin, Yu-Ching Liao, Ya-Ting Chen, Hsin-Ying Tung
  • Publication number: 20220344133
    Abstract: A method for forming a layer includes following operations. A workpiece is received in an apparatus for deposition. The apparatus for deposition includes a chamber, a pedestal disposed in the chamber to accommodate the workpiece, and a ring disposed on the pedestal. The ring includes a ring body having a first top surface and a second top surface and a barrier structure disposed between the first top surface and the second top surface. A vertical distance is defined by a top surface of the barrier structure and a top surface of the workpiece. The vertical distance is between approximately 0 mm and approximately 50 mm. A target disposed in the apparatus for deposition is sputtered. A sputtered material is deposited onto a top surface of the workpiece to form a layer. The barrier structure alters an electrical density distribution during the depositing the sputter material.
    Type: Application
    Filed: July 12, 2022
    Publication date: October 27, 2022
    Inventors: HSIN-LIANG CHEN, WEN-CHIH WANG, CHIA-HUNG LIAO, CHENG-CHIEH CHEN, YI-MING YEH, HUNG-TING LIN, YUNG-YAO LEE
  • Publication number: 20220319981
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a fin structure formed over a substrate, and the fin structure includes a plurality of nanostructures stacked in a vertical direction. The semiconductor device structure includes a gate structure formed over the fin structure, and an S/D structure formed adjacent to the gate structure. The semiconductor device structure includes a first via formed adjacent to the S/D structure, and a first contact structure formed over the S/D structure. The semiconductor device structure includes a second contact structure formed below the S/D structure, and the first via is in direct contact with the first contact structure and the second contact structure.
    Type: Application
    Filed: March 30, 2021
    Publication date: October 6, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Ting CHUNG, Yi-Bo LIAO, Kuan-Lun CHENG
  • Publication number: 20220289759
    Abstract: A compound, which can act as inhibitors of protein kinases, especially Class III RTKs such as FLT3, PDGFR?, c-KIT and/or CSF-1R kinases, for the treatments of diseases or disorders mediated by such kinases, has a structure of formula (I): or a stereoisomer, a tautomer, a pharmaceutically acceptable salt, a binder of a Proteolysis-Targeting Chimera (PROTAC) thereof. The compound can be used in the treatments of diseases or conditions mediated by FLT3, PDGFR, c-KIT, and/or CSF-1R kinases, or mediated by a mutant kinase of FLT3, PDGFR, c-KIT, and/or CSF-1R kinases. Such diseases or conditions may include cancers, autoimmune diseases, and bone resorptive diseases.
    Type: Application
    Filed: August 22, 2020
    Publication date: September 15, 2022
    Applicant: DEVELOPMENT CENTER FOR BIOTECHNOLOGY
    Inventors: Shao-Zheng PENG, Chu-Bin LIAO, Hung-Jyun HUANG, Yuan-Ting CHO, Yi-Mei CHANG, Yu-Chih PAN
  • Patent number: 11422330
    Abstract: A driving mechanism for moving an optical element is provided, including a movable portion, a fixed portion, a driving assembly, and a first resilient element. The movable portion is for connecting the optical element. The movable portion is movable relative to the fixed portion. The driving assembly drives the movable portion to move relative to the fixed portion. The first resilient element has a board structure. The movable portion is movably connected to the fixed portion via the first resilient element. The fixed portion includes a connection surface, a restricting surface, and a recessed portion. At least a portion of the first resilient element is disposed on the connection surface. The restricting surface contacts and restricts the movable portion. The recessed portion is located between the connection surface and the restricting surface, wherein the recessed portion is lower than the connection surface and the restricting surface.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: August 23, 2022
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Bing-Ru Song, Yi-Ho Chen, Chia-Pin Hsu, Chih-Wei Weng, Shin-Hua Chen, Chien-Lun Huang, Chao-Chun Chang, Shou-Jen Liu, Kun-Shih Lin, Nai-Wen Hsu, Yu-Cheng Lin, Shang-Yu Hsu, Yu-Huai Liao, Yi-Hsin Nieh, Shih-Ting Huang, Kuo-Chun Kao, Fu-Yuan Wu
  • Patent number: 11424280
    Abstract: A solid-state image sensor with pixels each including a photoelectric conversion portion made of a second type doped semiconductor layer and a semiconductor material layer, and the second type doped semiconductor layer contacts a first type doped semiconductor substrate. An anti-reflective portion is provided with multiple micro pillars on the semiconductor material layer, wherein micro pillars are isolated by recesses extending into the photoelectric conversion portion, and the refractive index of the micro pillar gradually decreases from bottom to top and is smaller than the refractive index of the light-receiving portion of the semiconductor material layer.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: August 23, 2022
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Shih-Ping Lee, Yi-Ping Lin, Yu-Ching Liao, Ya-Ting Chen, Hsin-Ying Tung
  • Publication number: 20220246522
    Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first vertical structure and a second vertical structure formed over the substrate, and a conductive rail structure between the first and second vertical structures. A top surface of the conductive rail structure can be substantially coplanar with top surfaces of the first and the second vertical structures.
    Type: Application
    Filed: April 18, 2022
    Publication date: August 4, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Bo Liao, Wei Ju LEE, Cheng-Ting CHUNG, Hou-Yu CHEN, Chun-Fu CHENG, Kuan-Lun CHENG
  • Publication number: 20220208982
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a substrate; semiconductor layers over the substrate, wherein the semiconductor layers are separate from each other and are stacked up along a direction generally perpendicular to a top surface of the substrate; a dielectric feature over and separate from the semiconductor layers; and a gate structure wrapping around each of the semiconductor layers, the gate structure having a gate dielectric layer and a gate electrode layer, wherein the gate dielectric layer interposes between the gate electrode layer and the dielectric feature and the dielectric feature is disposed over at least a part of the gate electrode layer.
    Type: Application
    Filed: March 21, 2022
    Publication date: June 30, 2022
    Inventors: Cheng-Ting Chung, Yi-Bo Liao, Hou-Yu Chen, Kuan-Lun Cheng
  • Patent number: 10290710
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a first gradient layer, two source/drain structures, a second gradient layer, and a gate. The first gradient layer is disposed on the substrate. The two source/drain structures are separately disposed on the first gradient layer. The second gradient layer is disposed on the two source/drain structures and the first gradient layer, and a second portion of the second gradient layer directly contacts a first portion of the first gradient layer. The gate is disposed on the second gradient layer, between the two source/drain structures.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: May 14, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuo-Chih Lai, Ming-Chang Lu, Wei Chen, Hui-Lin Wang, Yi-Ting Liao, Chin-Fu Lin
  • Publication number: 20190074357
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a first gradient layer, two source/drain structures, a second gradient layer, and a gate. The first gradient layer is disposed on the substrate. The two source/drain structures are separately disposed on the first gradient layer. The second gradient layer is disposed on the two source/drain structures and the first gradient layer, and a second portion of the second gradient layer directly contacts a first portion of the first gradient layer. The gate is disposed on the second gradient layer, between the two source/drain structures.
    Type: Application
    Filed: September 5, 2017
    Publication date: March 7, 2019
    Inventors: Kuo-Chih Lai, Ming-Chang Lu, Wei Chen, Hui-Lin Wang, Yi-Ting Liao, Chin-Fu Lin
  • Patent number: 8954717
    Abstract: A system capable of booting through a Universal Serial Bus device includes a Universal Serial Bus port, an embedded controller, a platform control hub, and a basic input/output system. The embedded controller is used for generating a boot signal when the system is powered off and at least one Universal Serial Bus device is plugged into the Universal Serial Bus port. The platform control hub is woken up according to the boot signal. The basic input/output system has boot sequence setting values. The basic input/output system first starts to boot the at least one Universal Serial Bus device through the platform control hub according to the boot sequence setting values when the basic input/output system is woken up according to the boot signal.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: February 10, 2015
    Assignee: Wistron Corporation
    Inventor: Yi-Ting Liao
  • Publication number: 20130061030
    Abstract: A system capable of booting through a Universal Serial Bus device includes a Universal Serial Bus port, an embedded controller, a platform control hub, and a basic input/output system. The embedded controller is used for generating a boot signal when the system is powered off and at least one Universal Serial Bus device is plugged into the Universal Serial Bus port. The platform control hub is restored according to the boot signal. The basic input/output system has boot sequence setting values. The basic input/output system first starts to boot the at least one Universal Serial Bus device through the platform control hub according to the boot sequence setting values when the basic input/output system is restored according to the boot signal.
    Type: Application
    Filed: December 12, 2011
    Publication date: March 7, 2013
    Inventor: Yi-Ting Liao
  • Publication number: 20120124399
    Abstract: A power control method for a computer system is disclosed. The computer system establishes wireless connection with a handheld equipment via a wireless communication interface. The power control method includes receiving a sound signal transmitted from the handheld equipment via the wireless communication interface when the computer system operates in a shut-down state, recognizing the sound signal to generate a recognition result, and starting the computer system when the recognition result indicates that the sound signal conforms to a start command.
    Type: Application
    Filed: May 25, 2011
    Publication date: May 17, 2012
    Inventor: Yi-Ting Liao