Patents by Inventor Yiannis Moisiadis

Yiannis Moisiadis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11455442
    Abstract: Methods, systems, and computer program products are described for extracting electromagnetic characteristics from a large-scale integrated circuit. An input layout of the large-scale integrated circuit is received. The input layout includes a netlist having a plurality of segments. Groups of segments from the plurality of segments are identified based on magnetic coupling. A plurality of matrices are generated including a conductance matrix, a capacitance matrix, and an inductance matrix. Submatrices of the inductance matrix are based on the groups of segments. Each submatrix represents inductances among segments within one of the groups or representing inductances between a pair of the groups of segments. A simulation model is output based on the plurality of matrices for simulation of the large-scale integrated circuit.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: September 27, 2022
    Assignee: Ansys, Inc.
    Inventors: Konstantis Daloukas, Kostas Karouzakis, Yiannis Moisiadis, Dimitris Dakopoulos
  • Patent number: 10262094
    Abstract: In one embodiment, a circuit analysis method includes obtaining a netlist of a circuit, generating a reduced model from the netlist, using the reduced model to synthesize a noise compatible netlist, ensuring accurate DC behavior, and simulating the circuit using the synthesized netlist.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: April 16, 2019
    Assignee: Helic, Inc.
    Inventors: Yiannis Moisiadis, Nikolaos Mouravliansky, Konstantis Daloukas
  • Patent number: 9672318
    Abstract: In one embodiment, a circuit analysis method includes obtaining a netlist of a circuit, generating a reduced model from the netlist, using the reduced model to synthesize a positive netlist having no controlled current or voltage sources, unstamping the synthesized positive netlist, and simulating the circuit using the unstamped synthesized positive netlist.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: June 6, 2017
    Assignee: HELIC, INC.
    Inventors: Yiannis Moisiadis, Nikolaos Mouravliansky
  • Publication number: 20160378905
    Abstract: In one embodiment, a circuit analysis method includes obtaining a netlist of a circuit, generating a reduced model from the netlist, using the reduced model to synthesize a positive netlist having no controlled current or voltage sources, unstamping the synthesized positive netlist, and simulating the circuit using the unstamped synthesized positive netlist.
    Type: Application
    Filed: June 29, 2015
    Publication date: December 29, 2016
    Inventors: Yiannis Moisiadis, Nikolaos Mouravliansky
  • Publication number: 20160378889
    Abstract: In one embodiment, a circuit analysis method includes obtaining a netlist of a circuit, generating a reduced model from the netlist, using the reduced model to synthesize a noise compatible netlist, ensuring accurate DC behavior, and simulating the circuit using the synthesized netlist.
    Type: Application
    Filed: June 29, 2015
    Publication date: December 29, 2016
    Inventors: Yiannis Moisiadis, Nikolaos Mouravliansky, Konstantis Daloukas