Patents by Inventor Yibin Ye

Yibin Ye has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7423899
    Abstract: A SRAM device is provided having a plurality of memory cells. Each memory cell may include a plurality of transistors coupled in a cross-coupled inverter configuration. An NMOS transistor may be coupled to a body of the two PMOS transistors in the cross-coupled inverter configuration so as to apply a forward body bias to the PMOS transistors of the cross-coupled inverter configuration. A power control unit may control a supply voltage to each of the PMOS transistors as well as apply the switching signal to the NMOS transistor based on a STANDBY mode of the memory cell.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: September 9, 2008
    Assignee: Intel Corporation
    Inventors: Stephen H. Tang, Muhammad M. Khellah, Dinesh Somasekhar, Yibin Ye, Vivek K. De, James W. Tschanz
  • Patent number: 7403426
    Abstract: In some embodiments, a memory array is provided with cells that when written to or read from, can have modified supplies to enhance their read stability and/or write margin performance. Other embodiments may be disclosed and/or claimed.
    Type: Grant
    Filed: May 25, 2005
    Date of Patent: July 22, 2008
    Assignee: Intel Corporation
    Inventors: Fatih Hamzaoglu, Kevin Zhang, Nam Sung Kim, Muhammad M. Khellah, Dinesh Somasekhar, Yibin Ye, Vivek K. De, Bo Zheng
  • Patent number: 7397395
    Abstract: In general, in one aspect, the disclosure describes an apparatus inluding a representative majority voter gate to analyze bit transitions of a pluraility of bits. The plurailuty of bits are analzed in groups. The representative majority voter gate generates an invert signal based on the analysis. The apparatus further inludes a conditional inverter to apply the invert signal to the pluraility of bits.
    Type: Grant
    Filed: February 16, 2005
    Date of Patent: July 8, 2008
    Assignee: Intel Corporation
    Inventors: James W Tschanz, Mircea R. Stan, Muhammad M Khellah, Yibin Ye, Vivek K De
  • Publication number: 20080158932
    Abstract: For one disclosed embodiment, an integrated circuit may comprise a memory array on the integrated circuit and access control circuitry on the integrated circuit. The memory array may have a bit line with one or more resistors along the bit line and may have a plurality of memory cells coupled to the bit line at a plurality of locations along the bit line. At least one resistor along the bit line may be between two locations at which memory cells are coupled to the bit line. The access control circuitry may be to select a memory cell coupled to the bit line and to sense a signal on the bit line from the selected memory cell. Other embodiments are also disclosed.
    Type: Application
    Filed: December 28, 2006
    Publication date: July 3, 2008
    Inventors: Muhammad M. Khellah, Dinesh Somasekhar, Yibin Ye, Nam Sung Kim, Vivek De
  • Publication number: 20080162986
    Abstract: For one disclosed embodiment, an apparatus may comprise a memory cell to store a bit value, wherein the memory cell may lose the bit value in response to a memory access operation. The apparatus may also comprise first circuitry to detect whether the memory cell loses the bit value in response to the memory access operation and second circuitry to restore the bit value in the memory cell in response to detection that the memory cell loses the bit value. Other embodiments are also disclosed.
    Type: Application
    Filed: December 28, 2006
    Publication date: July 3, 2008
    Inventors: Nam Sung Kim, Muhammad Khellah, Yibin Ye, Dinesh Somasekhar, Vivek De
  • Patent number: 7391640
    Abstract: A dynamic random access memory includes a cell having a circuit between a floating-body transistor and a bit line. Activation of the circuit is controlled to provide isolation between the floating body and bit-line voltage both during write operations and during times when the cell is unselected. The added isolation improves performance, for example, by reducing the need for gate-to-body coupling and the magnitude of voltage swings between the bit lines.
    Type: Grant
    Filed: December 10, 2004
    Date of Patent: June 24, 2008
    Assignee: Intel Corporation
    Inventors: Stephen H. Tang, Ali Keshavarzi, Dinesh Somasekhar, Fabrice Paillet, Muhammad M. Khellah, Yibin Ye, Shih-Lien L. Lu, Vivek K. De
  • Patent number: 7385865
    Abstract: In one embodiment, a memory array is provided comprising one or more columns each comprising a plurality of bit cells divided into groups of bit cells with each group of bit cells controllably coupled to a separate bit line.
    Type: Grant
    Filed: December 1, 2004
    Date of Patent: June 10, 2008
    Assignee: Intel Corporation
    Inventors: Muhammad M. Khellah, Dinesh Somasekhar, Yibin Ye, Gunjan H. Pandya, Vivek K. De
  • Patent number: 7355246
    Abstract: Some embodiments provide a memory cell comprising a body region doped with charge carriers of a first type, a source region disposed in the body region and doped with charge carriers of a second type, and a drain region disposed in the body region and doped with charge carriers of the second type. According to some embodiments, the body region, the source region, and the drain region are oriented in a first direction, the body region and the source region form a first junction, and the body region and the drain region form a second junction. Moreover, a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased. Some embodiments further include a transistor oriented in a second direction, wherein the second direction is not parallel to the first direction.
    Type: Grant
    Filed: November 7, 2005
    Date of Patent: April 8, 2008
    Assignee: Intel Corporation
    Inventors: Ali Keshavarzi, Stephen H. Tang, Dinesh Somasekhar, Fabrice Paillet, Muhammad M. Khellah, Yibin Ye, Shih-Lien L. Lu, Vivek K. De
  • Publication number: 20080082899
    Abstract: For one disclosed embodiment, an apparatus comprises memory circuitry including memory cells, error detection circuitry to detect error in data stored by memory cells of the memory circuitry, and supply voltage control circuitry to increase supply voltage for one or more memory cells of the memory circuitry based at least in part on detected error. Other embodiments are also disclosed.
    Type: Application
    Filed: September 29, 2006
    Publication date: April 3, 2008
    Inventors: Khellah Muhammad, Dinesh Somasekhar, Yibin Ye, Nam Sung Kim, Vivek De
  • Publication number: 20080080266
    Abstract: A memory line driver system may include a first input line to receive a clock-gated signal associated with a first supply power level, a second input line to receive an information signal associated with a second supply power level, and an output to drive a memory cell line according to the first supply power level based on the clock-gated signal and the information signal.
    Type: Application
    Filed: September 27, 2006
    Publication date: April 3, 2008
    Inventors: Muhammad M. Khellah, Dinesh Somasekhar, Yibin Ye, Nam Sung Kim, Vivek K. De
  • Patent number: 7342845
    Abstract: An apparatus and method are provided for limiting a drop of a supply voltage in an SRAM device to retain the state of the memory during an IDLE state. The apparatus may include a memory array, a sleep device, and a clamping circuit. The clamping circuit may be configured to activate the sleep device when a voltage drop across the memory array falls below a preset voltage and the memory array is in an IDLE state.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: March 11, 2008
    Assignee: Intel Corporation
    Inventors: Dinesh Somasekhar, Muhammad M. Khellah, Yibin Ye, Vivek K. De, James W. Tschanz, Stephen H. Tang
  • Patent number: 7326972
    Abstract: A device includes an interconnect structure having a number of circuit paths to transfer signals. The circuit paths transfer the signals at different speed to reduce the coupling capacitance effect between adjacent circuit paths.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: February 5, 2008
    Assignee: Intel Corporation
    Inventors: Maged M. Ghoneima, Muhammad M. Khellah, James W. Tschanz, Yibin Ye, Vivek K. De
  • Patent number: 7321502
    Abstract: A method is described that induced dielectric breakdown within a capacitor's dielectric material while driving a current through the capacitor. The current is specific to data that is being written into the capacitor. The method also involves reading the data by interpreting behavior of the capacitor that is determined by the capacitor's resistance, where, the capacitor's resistance is a consequence of the inducing and the driving.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: January 22, 2008
    Assignee: Intel Corporation
    Inventors: Fabrice Paillet, Ali Keshavarzi, Muhammad M. Khellah, Dinesh Somasekhar, Yibin Ye, Stephen H. Tang, Alavi Mohsen, Vivek K. De
  • Patent number: 7307899
    Abstract: A method and apparatus for reducing power consumption in integrated memory devices is provided. Banks of memory cells may be individually put into “sleep” mode via respective “sleep” transistors.
    Type: Grant
    Filed: May 23, 2005
    Date of Patent: December 11, 2007
    Assignee: Intel Corporation
    Inventors: Muhammad M. Khellah, Dinesh Somasekhar, Yibin Ye, Vivek K. De, James W. Tschanz, Stephen H. Tang
  • Patent number: 7295474
    Abstract: A cell in an information storage cell array is written, by asserting a signal on a bit line that is coupled to the cell and to a group of other cells in the array, to a first voltage. The cell is read by asserting a signal on a word line that is coupled to the cell and to another group of cells in the array, in a direction of, but without reaching, the first voltage. Other embodiments are also described and claimed.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: November 13, 2007
    Assignee: Intel Corporation
    Inventors: Yibin Ye, Muhammad M. Khellah, Dinesh Somasekhar, Ali Keshavarzi, Fabrice Paillet, Vivek K. De
  • Patent number: 7280425
    Abstract: A one-time programmable (OTP) cell includes an access transistor coupled to an antifuse transistor. Access transistor has a gate oxide thickness that is greater than the gate oxide thickness of the antifuse transistor so that if the antifuse transistor is programmed, the voltage felt across the gate/drain junction of the access transistor is insufficient to cause the gate oxide of the access transistor to break down. The dual gate oxide OTP cell may be used in an array in which only one OTP cell is programmed at a time. The dual gate oxide OTP cell also may be used in an array in which several OTP cells are programmed simultaneously.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: October 9, 2007
    Assignee: Intel Corporation
    Inventors: Ali Keshavarzi, Fabrice Paillet, Muhammad M. Khellah, Dinesh Somasekhar, Yibin Ye, Stephen H. Tang, Mohsen Alavi, Vivek K. De
  • Patent number: 7262107
    Abstract: A manufacturing process modification is disclosed for producing a metal-insulator-metal (MIM) capacitor. The MIM capacitor may be used in memory cells, such as DRAMs, and may also be integrated into logic processing, such as for microprocessors. The processing used to generate the MIM capacitor is adaptable to current logic processing techniques. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: August 28, 2007
    Assignee: Intel Corporation
    Inventors: Stephen H. Tang, Ali Keshavarzi, Dinesh Somasekhar, Fabrice Paillet, Muhammad M. Khellah, Yibin Ye, Shih-Lien L. Lu, Vivek K. De
  • Patent number: 7246215
    Abstract: A short latency and high bandwidth memory includes a systolic memory that is sub-divided into a plurality of memory arrays, including banks and pipelines that access these banks. Shorter latency and faster performance is achieved with this memory, because each bank is smaller in size and is accessed more rapidly. A high throughput rate is accomplished because of the pipelining. Memory is accessed at the pipeline frequency with the proposed read and write mechanism. Design complexity is reduced because each bank within the memory is the same and repeated. The memory array size is re-configured and organized to fit within desired size and area parameters.
    Type: Grant
    Filed: November 26, 2003
    Date of Patent: July 17, 2007
    Assignee: Intel Corporation
    Inventors: Shih-Lien L. Lu, Dinesh Somasekhar, Yibin Ye
  • Patent number: 7236410
    Abstract: A system includes a pull-up circuit to program a memory cell. The pull-up circuit may include a level shifter to receive a control signal, a supply voltage, and one or more of a plurality of rail voltages, each of the plurality of rail voltages substantially equal to a respective integer multiple of the supply voltage, and to generate a second control signal, and a cascode stage. The cascode stage may include a plurality of transistors, a gate voltage of each of the plurality of transistors to be controlled at least in part by a respective one of the second control signal, the supply voltage, and at least one of the plurality of rail voltages, and an output node to provide a cell programming signal.
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: June 26, 2007
    Assignee: Intel Corporation
    Inventors: Gerhard Schrom, Fabrice Paillet, Tanay Karnik, Dinesh Somasekhar, Yibin Ye, Ali Keshavarzi, Muhammad M. Khellah, Vivek K. De
  • Patent number: 7230846
    Abstract: In general, in one aspect, the disclosure describes a memory array including a plurality of memory cells arranged in rows and columns. Each memory cell includes a transistor having a floating body capable of storing a charge. A plurality of word lines and purge lines are interconnected to rows of memory cells. A plurality of bit lines are interconnected to columns of memory cells. Driving signals provided via the word lines, the purge lines, and the bit lines can cooperate to alter the charge of the floating body region in one or more of the memory cells.
    Type: Grant
    Filed: June 14, 2005
    Date of Patent: June 12, 2007
    Assignee: Intel Corporation
    Inventors: Ali Keshavarzi, Stephen H Tang, Dinesh Somasekhar, Fabrice Paillet, Muhammad M Khellah, Yibin Ye, Vivek K De, Gerhard Schrom