Abstract: In some embodiments, the invention includes an integrated circuit including a bitline and a bitline#, wordlines, and memory cells. The memory cells each corresponding to one of the wordlines and each include first and second pass transistors coupled between first and second storage nodes, respectively, and the bitline and bitline#, respectively, the corresponding wordline being coupled to gates of the first and second pass transistors. The memory cells include first and second inverters cross-coupled between the first and second storage nodes, wherein the first and second pass transistors each have a lower threshold voltage than do transistors of the first and second inverters. Wordline voltage control circuitry coupled to the wordlines selectively controls wordline signals on the wordlines.

Abstract: Reduction of standby leakage current in an internal circuit block using a transistor stack effect. For one embodiment, an apparatus includes a standby leakage reduction circuit to be coupled to the circuit block including a plurality of logic gates. The standby leakage reduction circuit causes a stack effect at each of the plurality of logic gates during a standby mode of the circuit block by turning off two or more series-coupled transistors of a same type (either n-type or p-type) at each of the plurality of logic gates.

Abstract: Alternately skewed gates to reduce signal transmission delay. For one embodiment, an integrated circuit includes a chain of gates alternately skewed for fast rise and fast fall. Pulse encoding logic coupled to the chain of gates pulse encodes a signal to be provided to and transmitted by the chain of alternately skewed gates.

Abstract: A method and an apparatus for generating oscillating waveforms using adiabatic circuitry. In one embodiment, an LC oscillating circuit generates oscillating waveforms that are replenished with replenishing circuitry. The replenishing circuitry includes enable circuitry and circuitry that reduces short circuit currents that may flow through the replenishing circuit. Furthermore, the pull-up and pull-down devices of the replenishing circuit are gradually turned on and gradually turned off to reduce the introduction of glitches into the oscillating sinusoidal waveform of the oscillating circuit. A control circuit, such as a phase lock loop circuit, is included with the present invention to receive an external clock reference waveform and match the frequency and phase of the oscillating waveform in the oscillating circuit to the external clock reference waveform.