Abstract: A method including managing downloading of at least two firmware functions, which are accessible by more than one driver, with one processor.

Abstract: A system including at least two processing units embedded on a chip able to communicate with each other and to generally independently control access to data from memory on the chip.

Abstract: According to some embodiments, time information is associated with data received at a digital signal processor based physical layer processing unit.

Abstract: A system including at least two processing units embedded on a chip able to communicate with each other and to generally independently control access to data from memory on the chip.

Abstract: A method including managing downloading of at least two firmware functions, which are accessible by more than one driver, with one processor.

Abstract: A relatively small FIFO queue is located on a semiconductor chip receiving and transmitting data in a computer system, typically a computer network. The FIFO queue has additional storage capability in the form of an expansion into the local memory of the computer system. The front and back ends of the FIFO, which are involved in receiving and transmitting data, are implemented on the chip. The FIFO expands into the space provided in the local memory only when the on-chip portion of the FIFO is full. The middle portion of the FIFO resides in expansion in the local memory. The local memory is accessed only in bursts of multiple credits, both for read transactions and for write transactions.

Abstract: A method providing automating detection of configuration between an adapter device and a DRAM device. Such a method a determines, in the adapter memory, the DRAM configuration, making it easier to change DRAM configuration in an existing board without the need to modify configuration pins in the existing board. A method for determining a configuration type in an Asynchronous Transfer Mode (ATM) communications network comprising the steps of providing an ATM adapter, the ATM adapter having an ATM adapter memory, providing a DRAM device, the DRAM device having a DRAM configuration, providing a link to connect the ATM adapter and the DRAM device, assuming, in the ATM adapter memory, a first DRAM configuration, verifying the step of assuming, and repeating the steps of assuming and verifying until the first DRAM configuration is determined.