Abstract: Accordingly, there are disclosed herein active cables and methods that enable direct connection between different generations of network interface ports or ports supporting different standards. One illustrative embodiment is an active 1:N breakout cable that includes a unary end connector connected by electrical conductors to each of multiple split end connectors. The unary end connector is adapted to fit into a network interface port of a primary host device to provide output PAM4 electrical signals that convey a multi-lane outbound data stream to the primary host device and to accept input PAM4 electrical signals that convey multi-lane inbound data stream from the primary host device.

Abstract: A cable, a manufacturing method, and a usage method, each facilitate product development, testing, and debugging. An illustrative embodiment of a cable manufacturing method includes: connecting a first connector plug to a first data recovery and re-modulation (DRR) device and to a first controller device; and coupling electrical signal conductors to the first DRR device to convey electrical transit signals to and from a second DRR device, the second DRR device being connected to a second connector plug. The first controller device is operable in response to a host command to initiate a debug dump by the first DRR device and to store the debug dump in a nonvolatile memory.

Abstract: An illustrative spread spectrum clocking (SSC) converter includes: a deserializer to receive a data stream with an unmodulated clock; a memory coupled to the deserializer to buffer the data stream; and a serializer coupled to the memory to retransmit the data stream with a spread spectrum clock. One illustrative conversion method, which may be implemented on a monolithic integrated circuit device, includes: receiving a data stream from an external transmitter in an unmodulated clock domain; storing the data stream in a buffer; and retransmitting the data stream with a spread spectrum clock. Such converters and methods may be employed in an illustrative system having: a test module to generate test data streams and to analyze result data streams for verifying operation of one or more devices under test in a spread spectrum clock domain as the test module operates in an unmodulated clock domain.

Abstract: An illustrative spread spectrum clocking (SSC) converter includes: a deserializer to receive a data stream with an unmodulated clock; a memory coupled to the deserializer to buffer the data stream; and a serializer coupled to the memory to retransmit the data stream with a spread spectrum clock. One illustrative conversion method, which may be implemented on a monolithic integrated circuit device, includes: receiving a data stream from an external transmitter in an unmodulated clock domain; storing the data stream in a buffer; and retransmitting the data stream with a spread spectrum clock. Such converters and methods may be employed in an illustrative system having: a test module to generate test data streams and to analyze result data streams for verifying operation of one or more devices under test in a spread spectrum clock domain as the test module operates in an unmodulated clock domain.

Abstract: Methods are disclosed for designing a tibial implant to minimize cortical impingement of a keel or other fixation structure when the tibial implant is implanted in the tibia bone. The design of the keel or other fixation structure on the tibial baseplate can be based on determining a common area between defined cancellous regions of at least two tibia bones. Methods are disclosed for designing a femoral component having a stem extension such that the stem can be sufficiently placed in the diaphysis of the femur when the femoral component is implanted. The method includes determining a canal axis in a femur that creates adequate engagement between a reamer and the diaphysis of the femur.

Abstract: A method for testing operation of a device under test (DUT) includes receiving an input bit stream at an input pin, the input bit stream including multiplexed test patterns for a plurality of scan chains of the DUT. The method further includes demultiplexing the multiplexed test patterns, and providing a corresponding test pattern data to each of the plurality of scan chains. The method further includes, at each of the plurality of scan chains, scanning test results from the scan chain, to produce multiplex output test data into an output bit stream.

Abstract: Ethernet link extension methods and devices provide, in one illustrative embodiment, an Ethernet link extender with physical medium attachment (PMA) circuits each having a transmitter and receiver that communicate with a respective node in a sequence of communication phases. The sequence includes at least an auto-negotiation phase and a subsequent training phase, the phases occurring simultaneously for both PMA circuits. In the auto-negotiation phase, the PMA circuits operate in a pass-through mode, rendering the extender transparent to the two nodes. In the training phase, the PMA circuits operate independently, sending training frames to their respective nodes based in part on received back-channel information and locally-determined training status information. The training phases may be prolonged if needed to provide a simultaneous transition to a frame-forwarding phase of the sequence.

Abstract: Accordingly, there are disclosed herein active cables and methods that enable direct connection between different generations of network interface ports or ports supporting different standards. One illustrative embodiment is an active 1:N breakout cable that includes a unary end connector connected by electrical conductors to each of multiple split end connectors. The unary end connector is adapted to fit into a network interface port of a primary host device to provide output PAM4 electrical signals that convey a multi-lane outbound data stream to the primary host device and to accept input PAM4 electrical signals that convey multi-lane inbound data stream from the primary host device.

Abstract: Ethernet link extension methods and devices provide, in one illustrative embodiment, an Ethernet link extender with physical medium attachment (PMA) circuits each having a transmitter and receiver that communicate with a respective node in a sequence of communication phases. The sequence includes at least an auto-negotiation phase and a subsequent training phase, the phases occurring simultaneously for both PMA circuits. In the auto-negotiation phase, the PMA circuits operate in a pass-through mode, rendering the extender transparent to the two nodes. In the training phase, the PMA circuits operate independently, sending training frames to their respective nodes based in part on received back-channel information and locally-determined training status information. The training phases may be prolonged if needed to provide a simultaneous transition to a frame-forwarding phase of the sequence.

Abstract: Accordingly, there are disclosed herein active cables and methods that enable direct connection between different generations of network interface ports or ports supporting different standards. One illustrative embodiment is an active 1:N breakout cable that includes a unary end connector connected by electrical conductors to each of multiple split end connectors. The unary end connector is adapted to fit into a network interface port of a primary host device to provide output PAM4 electrical signals that convey a multi-lane outbound data stream to the primary host device and to accept input PAM4 electrical signals that convey multi-lane inbound data stream from the primary host device.

Abstract: Integrated circuits such as multi-channel receivers may require loop inductors resistant to electromagnetic field interference. Such loop inductors may include multiple non-overlapping loops each defining a corresponding dipole, the multiple dipoles summing to zero, with at least one of said loops having unequal areas. The multiple non-overlapping loops may include: a center loop defining a central magnetic dipole; and a plurality of peripheral loops equally spaced around a perimeter of the center loop, each peripheral loop defining a peripheral magnetic dipole oriented opposite the central magnetic dipole, the plurality of peripheral loops substantially canceling a field from the central magnetic dipole. The total number of loops may be odd, with particular embodiments of three, five, and seven loop designs disclosed. Single and multi-turn embodiments are provided.

Abstract: A cable, a manufacturing method, and a communications method, employing preset transmit-side equalization to provide enhanced performance and/or to reduce receive-side equalization requirements. One illustrative cable embodiment includes: a first data recovery and re-modulation (DRR) device that exchanges inbound and outbound multi-lane data streams with a first host interface port via a first end connector plug; a second DRR device that exchanges inbound and outbound multi-lane data streams with a second host interface port via a second end connector plug; and electrical conductors connecting the first and second DRR devices to convey electrical transit signals therebetween. The first DRR device converts between said electrical transit signals and said inbound and outbound multi-lane data streams for the first host interface port, and the second DRR device converts between said electrical transit signals and said inbound and outbound multi-lane data streams for the second host interface port.

Abstract: A cable, a manufacturing method, and a communications method, employing preset transmit-side equalization to provide enhanced performance and/or to reduce receive-side equalization requirements. One illustrative cable embodiment includes: a first data recovery and re-modulation (DRR) device that exchanges inbound and outbound multi-lane data streams with a first host interface port via a first end connector plug; a second DRR device that exchanges inbound and outbound multi-lane data streams with a second host interface port via a second end connector plug; and electrical conductors connecting the first and second DRR devices to convey electrical transit signals therebetween. The first DRR device converts between said electrical transit signals and said inbound and outbound multi-lane data streams for the first host interface port, and the second DRR device converts between said electrical transit signals and said inbound and outbound multi-lane data streams for the second host interface port.

Abstract: A cable, a manufacturing method, and a usage method, each facilitate product development, testing, and debugging. An illustrative embodiment of a cable manufacturing method includes: connecting a first connector plug to a first data recovery and re-modulation (DRR) device and to a first controller device; and coupling electrical signal conductors to the first DRR device to convey electrical transit signals to and from a second DRR device, the second DRR device being connected to a second connector plug. The first controller device is operable in response to a host command to initiate a debug dump by the first DRR device and to store the debug dump in a nonvolatile memory.

Abstract: Disclosed microelectronic assemblies employ an integrated interposer cage to reduce electromagnetic interference with (and from) high-frequency components. One illustrative embodiment includes: at least one IC die having drive cores for a plurality of oscillators, the IC die attached in a flip-chip configuration to a (interposer) substrate, the substrate having: multiple inductors electrically coupled to said drive cores and each enclosed within a corresponding conductive cage integrated into the substrate to reduce mutual coupling between the inductors and noise coupled through substrate.

Abstract: Accordingly, there are disclosed herein active cables and methods that enable direct connection between different generations of network interface ports or ports supporting different standards. One illustrative embodiment is an active 1:N breakout cable that includes a unary end connector connected by electrical conductors to each of multiple split end connectors. The unary end connector is adapted to fit into a network interface port of a primary host device to provide output PAM4 electrical signals that convey a multi-lane outbound data stream to the primary host device and to accept input PAM4 electrical signals that convey multi-lane inbound data stream from the primary host device.

Abstract: Disclosed microelectronic assemblies employ an integrated interposer cage to reduce electromagnetic interference with (and from) high-frequency components. One illustrative embodiment includes: at least one IC die having drive cores for a plurality of oscillators, the IC die attached in a flip-chip configuration to a (interposer) substrate, the substrate having: multiple inductors electrically coupled to said drive cores and each enclosed within a corresponding conductive cage integrated into the substrate to reduce mutual coupling between the inductors and noise coupled through substrate.

Abstract: A circuit design verification method suitable for use with a 2.5D transceiver device potentially having hundreds of dice mounted on an interposer. An illustrative method includes: (a) retrieving a design of a circuit that includes multiple integrated circuit dice connected via an interposer, each die having at least one contact for receiving or transmitting a digital signal conveyed by an interchip connection of the interposer, said circuit including an IO cell for each such contact; (b) obtaining a timing model for components of said circuit, the timing model accounting for propagation delays of said IO cells and propagation delays of said interchip connections; (c) performing a static timing analysis of the design using the timing model to determine data required times and data arrival times at each of said components; (d) comparing the data required times with the data arrival times to detect timing violations; and (e) reporting said timing violations.

Abstract: Methods are disclosed for designing a tibial implant to minimize cortical impingement of a keel or other fixation structure when the tibial implant is implanted in the tibia bone. The design of the keel or other fixation structure on the tibial baseplate can be based on determining a common area between defined cancellous regions of at least two tibia bones. Methods are disclosed for designing a femoral component having a stem extension such that the stem can be sufficiently placed in the diaphysis of the femur when the femoral component is implanted. The method includes determining a canal axis in a femur that creates adequate engagement between a reamer and the diaphysis of the femur.

Abstract: A device includes a first die including a pseudo-random binary sequence (“PRBS”) generator that outputs test signals on parallel lanes. The device further includes a second die comprising a PRBS checker that compares at least a portion of the test signals with reference signals to identify a particular lane associated with an error.