Patents by Inventor Yih-Jenn Jiang

Yih-Jenn Jiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220189900
    Abstract: An electronic package is provided and includes at least one conductor with a relatively large width formed on an electrode pad of an electronic element and in contact with a circuit layer. As such, when the electronic element and the circuit layer deviate in position relative to one another, the circuit layer will be still in contact with the conductor and hence electrically connected to the electronic element.
    Type: Application
    Filed: February 9, 2021
    Publication date: June 16, 2022
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chia-Yu Kuo, Rui-Feng Tai, Yih-Jenn Jiang, Don-Son Jiang, Chang-Fu Lin
  • Publication number: 20220148996
    Abstract: An electronic package is provided, where a circuit layer and a metal layer having a plurality of openings are formed on a dielectric layer of a circuit portion to reduce the area ratio of the metal layer to the dielectric layer, so as to reduce stress concentration and prevent warping of the electronic package.
    Type: Application
    Filed: December 28, 2020
    Publication date: May 12, 2022
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Fang-Lin Tsai, Chia-Yu Kuo, Pei-Geng Weng, Wei-Son Tsai, Yih-Jenn Jiang
  • Publication number: 20190214372
    Abstract: An electronic package is provided, including: a first circuit structure; an electronic component and a conductive pillar disposed on the first circuit structure; an encapsulation layer encapsulating the electronic component and the conductive pillar; a second circuit structure disposed on the encapsulation layer; and a shielding layer encapsulating the first circuit structure, a side surface of the encapsulation layer, and a side surface of the second circuit structure. The electronic component is surrounded by the shielding layer, and is protected from electromagnetic interference. A method for fabricating the electronic package is also provided.
    Type: Application
    Filed: March 18, 2019
    Publication date: July 11, 2019
    Inventors: Hong-Da Chang, Yih-Jenn Jiang
  • Patent number: 10192838
    Abstract: A packaging substrate includes a base body having at least a conductive pad on a surface thereof, a dielectric layer formed on the surface of the base body and having at least a first opening for exposing the conductive pad and at least a second opening formed at a periphery of the first opening, and a metal layer formed on the conductive pad and the dielectric layer and extending to a sidewall of the second opening, thereby effectively eliminating side-etching of the metal layer under a solder bump.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: January 29, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chien-Lung Chuang, Po-Yi Wu, Meng-Tsung Lee, Yih-Jenn Jiang
  • Publication number: 20180068983
    Abstract: An electronic package is provided, including: a first circuit structure; an electronic component and a conductive pillar disposed on the first circuit structure; an encapsulation layer encapsulating the electronic component and the conductive pillar; a second circuit structure disposed on the encapsulation layer; and a shielding layer encapsulating the first circuit structure, a side surface of the encapsulation layer, and a side surface of the second circuit structure. The electronic component is surrounded by the shielding layer, and is protected from electromagnetic interference. A method for fabricating the electronic package is also provided.
    Type: Application
    Filed: April 24, 2017
    Publication date: March 8, 2018
    Inventors: Hong-Da Chang, Yih-Jenn Jiang
  • Publication number: 20170133337
    Abstract: A packaging substrate includes a base body having at least a conductive pad on a surface thereof, a dielectric layer formed on the surface of the base body and having at least a first opening for exposing the conductive pad and at least a second opening formed at a periphery of the first opening, and a metal layer formed on the conductive pad and the dielectric layer and extending to a sidewall of the second opening, thereby effectively eliminating side-etching of the metal layer under a solder bump.
    Type: Application
    Filed: January 20, 2017
    Publication date: May 11, 2017
    Inventors: Chien-Lung Chuang, Po-Yi Wu, Meng-Tsung Lee, Yih-Jenn Jiang
  • Patent number: 8895367
    Abstract: A semiconductor package includes: a chip having an active surface with a plurality of electrode pads and an inactive surface opposite to the active surface; an encapsulant encapsulating the chip and having opposite first and second surfaces, the first surface being flush with the active surface of the chip; and first and second metal layers formed on the second surface of the encapsulant, thereby providing a rigid support to the overall structure to prevent warpage and facilitating heat dissipation of the overall structure.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: November 25, 2014
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Jung-Pang Huang, Hui-Min Huang, Kuan-Wei Chuang, Chun-Tang Lin, Yih-Jenn Jiang
  • Publication number: 20130330883
    Abstract: A semiconductor package includes: a chip having an active surface with a plurality of electrode pads and an inactive surface opposite to the active surface; an encapsulant encapsulating the chip and having opposite first and second surfaces, the first surface being flush with the active surface of the chip; and first and second metal layers formed on the second surface of the encapsulant, thereby providing a rigid support to the overall structure to prevent warpage and facilitating heat dissipation of the overall structure.
    Type: Application
    Filed: August 12, 2013
    Publication date: December 12, 2013
    Applicant: Siliconware Precision Industries Co., Ltd.
    Inventors: Jung-Pang Huang, Hui-Min Huang, Kuan-Wei Chuang, Chun-Tang Lin, Yih-Jenn Jiang
  • Patent number: 8519526
    Abstract: A semiconductor package includes: a chip having an active surface with a plurality of electrode pads and an inactive surface opposite to the active surface; an encapsulant encapsulating the chip and having opposite first and second surfaces, the first surface being flush with the active surface of the chip; and first and second metal layers formed on the second surface of the encapsulant, thereby providing a rigid support to the overall structure to prevent warpage and facilitating heat dissipation of the overall structure.
    Type: Grant
    Filed: May 20, 2011
    Date of Patent: August 27, 2013
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Jung-Pang Huang, Hui-Min Huang, Kuan-Wei Chuang, Chun-Tang Lin, Yih-Jenn Jiang
  • Publication number: 20130113095
    Abstract: A packaging substrate includes a base body having at least a conductive pad on a surface thereof, a dielectric layer formed on the surface of the base body and having at least a first opening for exposing the conductive pad and at least a second opening formed at a periphery of the first opening, and a metal layer formed on the conductive pad and the dielectric layer and extending to a sidewall of the second opening, thereby effectively eliminating side-etching of the metal layer under a solder bump.
    Type: Application
    Filed: May 29, 2012
    Publication date: May 9, 2013
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chien-Lung Chuang, Po-Yi Wu, Meng-Tsung Lee, Yih-Jenn Jiang
  • Publication number: 20120161301
    Abstract: A semiconductor package includes: a chip having an active surface with a plurality of electrode pads and an inactive surface opposite to the active surface; an encapsulant encapsulating the chip and having opposite first and second surfaces, the first surface being flush with the active surface of the chip; and first and second metal layers formed on the second surface of the encapsulant, thereby providing a rigid support to the overall structure to prevent warpage and facilitating heat dissipation of the overall structure.
    Type: Application
    Filed: May 20, 2011
    Publication date: June 28, 2012
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Jung-Pang Huang, Hui-Min Huang, Kuan-Wei Chuang, Chun-Tang Lin, Yih-Jenn Jiang
  • Publication number: 20120129315
    Abstract: A method for fabricating a semiconductor package includes the steps of: providing an alignment board having a plurality of openings and a plurality of alignment marks corresponding to the openings, respectively; disposing a plurality of chips on the alignment board at positions corresponding to the openings according to the alignment marks; pressing the alignment board with a carrier board having a soft layer disposed on one surface thereof so as to embed the chips in the soft layer of the carrier board; and removing the alignment board. As such, the positions of the chips are accurately positioned according to the alignment marks on the alignment board.
    Type: Application
    Filed: January 12, 2011
    Publication date: May 24, 2012
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yeh-Chang Hu, Chung-Tang Lin, Hui-Min Huang, Yih-Jenn Jiang, Shih-Kuang Chiu
  • Patent number: 7993967
    Abstract: A semiconductor package and a fabrication method are disclosed. The fabrication method includes applying a sacrificial layer on one surface of a metal carrier, applying an insulation layer on the sacrificial layer, and forming through holes in the sacrificial layer and the insulation layer to expose the metal carrier; forming a conductive metallic layer in each through hole; forming a patterned circuit layer on the insulation layer to be electrically connected to the conductive metallic layer; mounting at least a chip on the insulation layer and electrically connecting the chip to the patterned circuit layer; forming an encapsulant to encapsulate the chip and the patterned circuit layer; and removing the metal carrier and the sacrificial layer to expose the insulation layer and conductive metallic layer to allow the conductive metallic layer to protrude from the insulation layer.
    Type: Grant
    Filed: November 12, 2009
    Date of Patent: August 9, 2011
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yih-Jenn Jiang, Han-Ping Pu, Chien-Ping Huang, Cheng-Hsu Hsiao
  • Publication number: 20100052146
    Abstract: A semiconductor package and a fabrication method are disclosed. The fabrication method includes applying a sacrificial layer on one surface of a metal carrier, applying an insulation layer on the sacrificial layer, and forming through holes in the sacrificial layer and the insulation layer to expose the metal carrier; forming a conductive metallic layer in each through hole; forming a patterned circuit layer on the insulation layer to be electrically connected to the conductive metallic layer; mounting at least a chip on the insulation layer and electrically connecting the chip to the patterned circuit layer; forming an encapsulant to encapsulate the chip and the patterned circuit layer; and removing the metal carrier and the sacrificial layer to expose the insulation layer and conductive metallic layer to allow the conductive metallic layer to protrude from the insulation layer.
    Type: Application
    Filed: November 12, 2009
    Publication date: March 4, 2010
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yih-Jenn Jiang, Han-Ping Pu, Chien-Ping Huang, Cheng-Hsu Hsiao
  • Patent number: 7638879
    Abstract: A semiconductor package and a fabrication method are disclosed. The fabrication method includes applying a sacrificial layer on one surface of a metal carrier, applying an insulation layer on the sacrificial layer, and forming through holes in the sacrificial layer and the insulation layer to expose the metal carrier; forming a conductive metallic layer in each through hole; forming a patterned circuit layer on the insulation layer to be electrically connected to the conductive metallic layer; mounting at least a chip on the insulation layer and electrically connecting the chip to the patterned circuit layer; forming an encapsulant to encapsulate the chip and the patterned circuit layer; and removing the metal carrier and the sacrificial layer to expose the insulation layer and conductive metallic layer to allow the conductive metallic layer to protrude from the insulation layer.
    Type: Grant
    Filed: November 16, 2007
    Date of Patent: December 29, 2009
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yih-Jenn Jiang, Han-Ping Pu, Chien-Ping Huang, Cheng-Hsu Hsiao
  • Publication number: 20080116580
    Abstract: A semiconductor package and a fabrication method are disclosed. The fabrication method includes applying a sacrificial layer on one surface of a metal carrier, applying an insulation layer on the sacrificial layer, and forming through holes in the sacrificial layer and the insulation layer to expose the metal carrier; forming a conductive metallic layer in each through hole; forming a patterned circuit layer on the insulation layer to be electrically connected to the conductive metallic layer; mounting at least a chip on the insulation layer and electrically connecting the chip to the patterned circuit layer; forming an encapsulant to encapsulate the chip and the patterned circuit layer; and removing the metal carrier and the sacrificial layer to expose the insulation layer and conductive metallic layer to allow the conductive metallic layer to protrude from the insulation layer.
    Type: Application
    Filed: November 16, 2007
    Publication date: May 22, 2008
    Applicant: Siliconware Precision Industries Co., Ltd.
    Inventors: Yih-Jenn Jiang, Han-Ping Pu, Chien-Ping Huang, Cheng-Hsu Hsiao
  • Publication number: 20070178627
    Abstract: A flip-chip semiconductor device and a method for fabricating the same are provided. A first underfill material with a low Young's modulus is applied to corners of a chip mounting area defined on a substrate. A chip is mounted on and electrically connected to the chip mounting area by a plurality of conductive bumps, allowing the first underfill material to encapsulate corners of the chip. A second underfill material with a high Young's modulus is used to fill a gap between the chip and the substrate to protect the conductive bumps and support the chip.
    Type: Application
    Filed: December 28, 2006
    Publication date: August 2, 2007
    Applicant: Siliconware Precision Industries Co., Ltd.
    Inventors: Yih Jenn Jiang, Han Ping Pu, Cheng Hsu Hsiao