Patents by Inventor Yin Chen

Yin Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230299005
    Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate having plurality of contacts, a plurality of composite plugs positioned above the plurality of contacts, a plurality of metal spacers positioned above the substrate; and a plurality of air gaps positioned above the substrate. At least one of the plurality of composite plugs includes a protection liner having a U-shaped profile and a metal plug in the protection liner, and the protection liner is in direct contact with one of the plurality of contacts.
    Type: Application
    Filed: March 18, 2022
    Publication date: September 21, 2023
    Inventor: TE-YIN CHEN
  • Publication number: 20230282706
    Abstract: In an embodiment, a device includes: a gate structure on a channel region of a substrate; a gate mask on the gate structure, the gate mask including a first dielectric material and an impurity, a concentration of the impurity in the gate mask decreasing in a direction extending from an upper region of the gate mask to a lower region of the gate mask; a gate spacer on sidewalls of the gate mask and the gate structure, the gate spacer including the first dielectric material and the impurity, a concentration of the impurity in the gate spacer decreasing in a direction extending from an upper region of the gate spacer to a lower region of the gate spacer; and a source/drain region adjoining the gate spacer and the channel region.
    Type: Application
    Filed: May 15, 2023
    Publication date: September 7, 2023
    Inventors: Wei-Ting Chien, Wen-Yen Chen, Li-Ting Wang, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang
  • Publication number: 20230282583
    Abstract: A semiconductor device includes a first dielectric layer disposed over a substrate and a conductive feature, a doped dielectric layer disposed over the first dielectric layer, a first metal portion disposed in the first dielectric layer and in contact with the conductive feature, and a doped metal portion disposed over the first metal portion. The first metal portion and the doped metal portion include a same noble metal material. The doped dielectric layer and the doped metal portion include same dopants. The dopants are bonded to the noble metal material.
    Type: Application
    Filed: April 18, 2023
    Publication date: September 7, 2023
    Inventors: Kuo-Ju Chen, Chun-Hsien Huang, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20230282751
    Abstract: A semiconductor structure includes a substrate and a stacked structure including channel layers interleaved with a metal gate structure. The semiconductor structure also includes an isolation feature disposed between the stacked structure and the substrate, where a bottommost portion of the metal gate structure directly contacts the isolation feature. The semiconductor structure further includes a source/drain feature disposed adjacent the stacked structure and an inner spacer disposed between the metal gate structure and the source/drain feature.
    Type: Application
    Filed: June 6, 2022
    Publication date: September 7, 2023
    Inventors: Chia-Cheng Chen, Yun Chen Teng, Liang-Yin Chen, Yee-Chia Yeo, Tsai-Jung Ho
  • Patent number: 11744762
    Abstract: A gait activity learning assistance system, and an application method thereof, includes a main body, at least one movement detecting module, a control module, at least one driving module and at least one dynamic measurement module. The system is able to guide and induce a user to learn gait autonomously by disposing at least one force-transmission unit on at least one limb position of the user, besides, the system is able to measure a dynamic change of the at least one force-transmission unit by the at least one dynamic measurement module while user receiving a gait assistance, and send them back to the control module immediately for a real-time analysis.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: September 5, 2023
    Assignee: National Yang Ming Chiao Tung University
    Inventors: Chung-Huang Yu, Fu-Cheng Wang, Po-Yin Chen, Hsiao-Kuan Wu, Yu-You Lin, Kai-Lin Wu
  • Patent number: 11742386
    Abstract: The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: August 29, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Su-Hao Liu, Huicheng Chang, Chia-Cheng Chen, Liang-Yin Chen, Kuo-Ju Chen, Chun-Hung Wu, Chang-Miao Liu, Huai-Tei Yang, Lun-Kuang Tan, Wei-Ming You
  • Patent number: 11742210
    Abstract: The present disclosure provides a method to enlarge the process window for forming a source/drain contact. The method may include receiving a workpiece that includes a source/drain feature exposed in a source/drain opening defined between two gate structures, conformally depositing a dielectric layer over sidewalls of the source/drain opening and a top surface of the source/drain feature, anisotropically etching the dielectric layer to expose the source/drain feature, performing an implantation process to the dielectric layer, and after the performing of the implantation process, performing a pre-clean process to the workpiece. The implantation process includes a non-zero tilt angle.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: August 29, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Han Chou, Kuan-Yu Yeh, Wei-Yip Loh, Hung-Hsu Chen, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20230268442
    Abstract: In accordance with some embodiments, a source/drain contact is formed by exposing a source/drain region through a first dielectric layer and a second dielectric layer. The second dielectric layer is recessed under the first dielectric layer, and a silicide region is formed on the source/drain region, wherein the silicide region has an expanded width.
    Type: Application
    Filed: April 18, 2023
    Publication date: August 24, 2023
    Inventors: Wei-Ting Chien, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
  • Patent number: 11736121
    Abstract: An error correction method comprises: when a decoder determines that an input analog code is at a forbidden state, setting a digital binary code as a first predetermined code and inputting the digital binary code to an ECC engine; determining whether the digital binary code has no error or two errors; when the digital binary code has no error, outputting the digital binary code after ECC by the ECC engine; when the digital binary code has two errors, resetting the digital binary code as a second predetermined code and inputting the digital binary code to the ECC engine for ECC; and when the decoder determines that the input analog code is not at the forbidden state, decoding the input analog code into the digital binary code and inputting the digital binary code to the ECC engine for ECC.
    Type: Grant
    Filed: May 27, 2022
    Date of Patent: August 22, 2023
    Assignee: ETRON TECHNOLOGY, INC.
    Inventors: Ho-Yin Chen, Han-Hsien Wang, Han-Nung Yeh
  • Publication number: 20230261048
    Abstract: A method includes depositing a multi-layer stack on a semiconductor substrate, the multi-layer stack including a plurality of sacrificial layers that alternate with a plurality of channel layers; forming a dummy gate on the multi-layer stack; forming a first spacer on a sidewall of the dummy gate; performing a first implantation process to form a first doped region, the first implantation process having a first implant energy and a first implant dose; performing a second implantation process to form a second doped region, where the first doped region and the second doped region are in a portion of the channel layers uncovered by the first spacer and the dummy gate, the second implantation process having a second implant energy and a second implant dose, where the second implant energy is greater than the first implant energy, and where the first implant dose is different from the second implant dose.
    Type: Application
    Filed: February 14, 2022
    Publication date: August 17, 2023
    Inventors: Yu-Chang Lin, Chun-Hung Wu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20230253243
    Abstract: A method includes forming a first dielectric layer over a source/drain region, and forming a source/drain contact plug over and electrically connecting to the source/drain region. A top portion of the source/drain contact plug has a first lateral dimension. An implantation process is performed to implant a dopant into the first dielectric layer. The implantation process results in the source/drain contact plug to have a second lateral dimension smaller than the first lateral dimension. The method further includes forming a second dielectric layer over the etch stop layer, and forming a gate contact plug adjacent to the source/drain contact plug.
    Type: Application
    Filed: March 27, 2023
    Publication date: August 10, 2023
    Inventors: Kuo-Ju Chen, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo, Meng-Han Chou
  • Patent number: 11718645
    Abstract: The instant invention describes macrocyclic compounds having therapeutic activity, and the mechanism and methods of treating disorders such as autoimmune diseases, inflammation, and cancer, tumors and cell proliferation related disorders.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: August 8, 2023
    Assignee: University of Florida Research Foundation, Incorporated
    Inventors: Hendrik Luesch, Qi-Yin Chen
  • Patent number: 11721762
    Abstract: A fin field effect transistor (FinFET) device structure and method for forming FinFET device structure are provided. The FinFET structure includes a substrate and an isolation structure formed on the substrate. The FinFET structure also includes a fin structure extending above the substrate, and the fin structure is embedded in the isolation structure. The FinFET structure further includes an epitaxial structure formed on the fin structure, the epitaxial structure has a pentagon-like shape, and an interface between the epitaxial structure and the fin structure is lower than a top surface of the isolation structure.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: August 8, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zhe-Hao Zhang, Tung-Wen Cheng, Che-Cheng Chang, Yung-Jung Chang, Chang-Yin Chen
  • Publication number: 20230242482
    Abstract: The invention is directed towards compounds (e.g., Formulae (I)-(IX)), their mechanism of action, processes to prepare the compounds, methods of activating quorum sensing signaling activity, and methods of treating diseases and disorders using the compounds described herein (e.g., Formulae (I)-(IX)).
    Type: Application
    Filed: July 24, 2020
    Publication date: August 3, 2023
    Applicants: University of Florida Research Foundation, Incorporated, Smithsonian Institution
    Inventors: Hendrik Luesch, Xiao Liang, Susan Matthew, Jason C. Kwan, Qi-Yin Chen, Valerie J. Paul
  • Patent number: 11710659
    Abstract: The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.
    Type: Grant
    Filed: December 27, 2021
    Date of Patent: July 25, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Li-Chieh Wu, Tang-Kuei Chang, Kuo-Hsiu Wei, Kei-Wei Chen, Ying-Lang Wang, Su-Hao Liu, Kuo-Ju Chen, Liang-Yin Chen, Huicheng Chang, Ting-Kui Chang, Chia Hsuan Lee
  • Patent number: 11709987
    Abstract: A method of generating an integrated circuit includes providing a placing layout of the integrated circuit; generating a routed layout of the integrated circuit, the routed layout includes a layout region with a systematic design rule check (DRC) violation; generating an adjusted routing layout of the integrated circuit by adjusting the layout region with the systematic DRC violation according to a target placement recipe in a plurality of placement recipes; extracting features of the placing layout to obtain an extracted data; extracting features of the layout region with the systematic DRC violation to obtain an extracted routing data; performing a training process upon the extracted data and the extracted routing data to generate a plurality of aggregated-cluster models; and selecting a target aggregated-cluster model from the plurality of aggregated-cluster models by comparing the extracted data to the plurality of aggregated-cluster models.
    Type: Grant
    Filed: July 27, 2021
    Date of Patent: July 25, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shih-Yao Lin, Yi-Lin Chuang, Yin-An Chen, Shih Feng Hong
  • Publication number: 20230230976
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a gate structure over a substrate. The semiconductor structure also includes a gate spacer on a sidewall of the gate structure. The semiconductor structure also includes a source/drain feature adjacent to the gate structure. The semiconductor structure also includes a doped region extending along a bottom surface of the gate spacer. The source/drain feature has a curved sidewall connecting a top surface of the doped region and a bottom surface of the doped region.
    Type: Application
    Filed: March 20, 2023
    Publication date: July 20, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Cheng CHEN, Chia-Ling CHAN, Liang-Yin CHEN, Huicheng CHANG
  • Patent number: 11705505
    Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a sacrificial gate structure over an active region. A first spacer layer is formed along sidewalls and a top surface of the sacrificial gate structure. A first protection layer is formed over the first spacer layer. A second spacer layer is formed over the first protection layer. A third spacer layer is formed over the second spacer layer. The sacrificial gate structure is replaced with a replacement gate structure. The second spacer layer is removed to form an air gap between the first protection layer and the third spacer layer.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: July 18, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Ting Chien, Liang-Yin Chen, Yi-Hsiu Liu, Tsung-Lin Lee, Huicheng Chang
  • Patent number: 11700720
    Abstract: The present application provides a memory device with an air gap. The memory device includes an active region disposed in a substrate; a word line disposed in the substrate, wherein the word line is intersected with the active region; a contact structure disposed on the substrate, wherein the contact structure is located at a side of the word line, and electrically connected to the active region; a first conductive layer and a second conductive layer disposed over the substrate, wherein the contact structure is covered by the first and second conductive layers; a conductive pillar overlapped with and electrically connected to the contact structure; a landing pad covers and electrically connects to the conductive pillar, wherein a sidewall of the conductive pillar is laterally recessed from a sidewall of the landing pad; and a dielectric layer laterally surrounding the conductive pillar and the landing pad.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: July 11, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Te-Yin Chen
  • Patent number: D997162
    Type: Grant
    Filed: December 5, 2020
    Date of Patent: August 29, 2023
    Assignee: ORIGIN WIRELESS, INC.
    Inventors: Chao-Lun Mai, Wang Yin Chen, Beibei Wang, Oscar Chi-Lim Au, K. J. Ray Liu