Patents by Inventor Yin-Fa Chen

Yin-Fa Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240014143
    Abstract: A semiconductor package structure includes a first redistribution layer, a second redistribution layer, a first semiconductor die, a second semiconductor die, an adhesive layer, and a molding material. The second redistribution layer is disposed over the first redistribution layer. The first semiconductor die and the second semiconductor die are stacked vertically between the first redistribution layer and the second redistribution layer. The first semiconductor die is electrically coupled to the first redistribution layer, and the second semiconductor die is electrically coupled to the second redistribution layer. The adhesive layer extends between the first semiconductor die and the second semiconductor die. The molding material surrounds the first semiconductor die, the adhesive layer, and the second semiconductor die.
    Type: Application
    Filed: June 8, 2023
    Publication date: January 11, 2024
    Inventors: Yi-Lin TSAI, Kun-Ting HUNG, Yin-Fa CHEN, Chi-Yuan CHEN, Wen-Sung HSU
  • Patent number: 11869831
    Abstract: A semiconductor package includes a die attach pad, a plurality of lead terminals positioned about the die attach pad and disposed along side edges of the semiconductor package, a semiconductor die mounted on the die attach pad, a molding compound encapsulating the plurality of lead terminals and the semiconductor die, and at least one dummy lead disposed in a corner region of the semiconductor package between the plurality of lead terminals.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: January 9, 2024
    Assignee: MEDIATEK INC.
    Inventors: Chin-Chiang Chang, Yin-Fa Chen, Shih-Chin Lin
  • Publication number: 20230389296
    Abstract: The present application provides a method of manufacturing a semiconductor device. The method includes steps of forming a substrate comprising a first island and a second island, wherein the first island has a first area, and the second island has a second area greater than the first area; depositing an insulative layer to cover the substrate; forming a storage node contact and a conductive feature penetrating through the insulative layer, wherein the storage node contact is in contact with the first island and the conductive feature is in contact with the second island; and forming a conductive line on the insulative layer and connected to the conductive feature.
    Type: Application
    Filed: May 26, 2022
    Publication date: November 30, 2023
    Inventors: YIN-FA CHEN, JUI-HSIU JAO
  • Publication number: 20230389285
    Abstract: The present application provides a semiconductor device and a semiconductor chip. The semiconductor device includes a substrate, a conductive line, a conductive feature and a plurality of memory cells. The substrate includes a first island, a second island and an isolation structure, and the isolation structure is disposed between the first island and the second island. The first island has a first area, and the second island has a second area greater than the first area. The conductive line is disposed over the substrate. The conductive feature connects the conductive line to the second island. The plurality of memory cells are disposed in or on the first island.
    Type: Application
    Filed: May 26, 2022
    Publication date: November 30, 2023
    Inventors: YIN-FA CHEN, JUI-HSIU JAO
  • Publication number: 20230389302
    Abstract: The present application provides a semiconductor device with a programmable feature. The semiconductor device includes a substrate, a conductive line, a conductive feature and a plurality of memory cells. The substrate includes a first island, a second island and an isolation structure, wherein the isolation structure is disposed between the first island and the second island. The first island has a first area, and the second island has a second area greater than the first area. The conductive line is disposed over the substrate. The conductive feature connects the conductive line to the second island. The plurality of memory cells are disposed in or on the first island.
    Type: Application
    Filed: May 26, 2022
    Publication date: November 30, 2023
    Inventors: YIN-FA CHEN, JUI-HSIU JAO
  • Publication number: 20230389272
    Abstract: The present application provides a method of manufacturing a semiconductor device. The method includes steps of providing a substrate comprising a first island and a second island, wherein the first island has a first area and the second island has a second area greater than the first area; depositing an insulative layer to cover the substrate; forming a conductive feature penetrating through the insulative layer and contacting the second island; and forming a conductive line on the insulative layer and connected to the conductive feature.
    Type: Application
    Filed: May 26, 2022
    Publication date: November 30, 2023
    Inventors: YIN-FA CHEN, JUI-HSIU JAO
  • Publication number: 20230282626
    Abstract: A high-bandwidth package-on-package (HBPoP) structure includes a first package structure and a second package structure disposed over the first package structure. The first package structure includes a first package substrate, a semiconductor die, an interposer, and a molding material. The first package substrate is formed of a silicon and/or ceramic material. The semiconductor die is disposed over the first package substrate. The interposer is disposed over the semiconductor die and is formed of a silicon and/or ceramic material. The molding material is disposed between the first package substrate and the interposer and surrounds the semiconductor die.
    Type: Application
    Filed: February 2, 2023
    Publication date: September 7, 2023
    Inventors: Tai-Yu CHEN, Bo-Jiun YANG, Tsung-Yu PAN, Yin-Fa CHEN, Ta-Jen YU, Bo-Hao MA, Wen-Sung HSU, Yao-Pang HSU
  • Publication number: 20230260866
    Abstract: A semiconductor package structure includes a package substrate, a semiconductor die, an interposer, an adhesive layer, and a molding material. The semiconductor die is disposed over the package substrate. The interposer is disposed over the semiconductor die. The adhesive layer connects the semiconductor die and the interposer. The molding material surrounds the semiconductor die and the adhesive layer.
    Type: Application
    Filed: January 20, 2023
    Publication date: August 17, 2023
    Inventors: Yin-Fa CHEN, Bo-Jiun YANG, Ta-Jen YU, Bo-Hao MA, Chih-Wei CHANG, Tsung-Yu PAN, Tai-Yu CHEN, Shih-Chin LIN, Wen-Sung HSU
  • Publication number: 20220115303
    Abstract: A semiconductor package includes a die attach pad, a plurality of lead terminals positioned about the die attach pad and disposed along side edges of the semiconductor package, a semiconductor die mounted on the die attach pad, a molding compound encapsulating the plurality of lead terminals and the semiconductor die, and at least one dummy lead disposed in a corner region of the semiconductor package between the plurality of lead terminals.
    Type: Application
    Filed: August 30, 2021
    Publication date: April 14, 2022
    Applicant: MEDIATEK INC.
    Inventors: Chin-Chiang Chang, Yin-Fa Chen, Shih-Chin Lin