Patents by Inventor Ying-Ho Chen
Ying-Ho Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240099994Abstract: Provided are sustained-release pharmaceutical compositions including a ketamine pamoate salt and a pharmaceutically acceptable carrier thereof. The compositions include aqueous suspension, solution and matrix delivery system, which can provide sustained release for anesthesia, analgesia or treatment of central nervous system and anti-inflammatory diseases.Type: ApplicationFiled: December 18, 2020Publication date: March 28, 2024Applicant: ALAR PHARMACEUTICALS INC.Inventors: Tong-Ho Lin, Yung-Shun Wen, Chai-Hsien Chen, Ying-Ting Liu, Rui-Zhi Hou, Zhi-Rong Wu
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Publication number: 20230386937Abstract: Disclosed is a method of forming a semiconductor device. The method includes providing a precursor having a substrate and gate stacks over the substrate, wherein each of the gate stacks includes an electrode layer, a first hard mask (HM) layer over the electrode layer, and a second HM layer over the first HM layer. The method further includes depositing a dielectric layer over the substrate and the gate stacks and filling spaces between the gate stacks; and performing a first chemical mechanical planarization (CMP) process to partially remove the dielectric layer. The method further includes performing an etching process to remove the second HM layer and to partially remove the dielectric layer, thereby exposing the first HM layer. The method further includes performing a second CMP process to at least partially remove the first HM layer.Type: ApplicationFiled: July 26, 2023Publication date: November 30, 2023Inventors: Yu-Jen Shen, Ying-Ho Chen, Yung-Cheng Lu
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Patent number: 11756838Abstract: Disclosed is a method of forming a semiconductor device. The method includes providing a precursor having a substrate and gate stacks over the substrate, wherein each of the gate stacks includes an electrode layer, a first hard mask (HM) layer over the electrode layer, and a second HM layer over the first HM layer. The method further includes depositing a dielectric layer over the substrate and the gate stacks and filling spaces between the gate stacks; and performing a first chemical mechanical planarization (CMP) process to partially remove the dielectric layer. The method further includes performing an etching process to remove the second HM layer and to partially remove the dielectric layer, thereby exposing the first HM layer. The method further includes performing a second CMP process to at least partially remove the first HM layer.Type: GrantFiled: July 30, 2021Date of Patent: September 12, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Jen Shen, Ying-Ho Chen, Yung-Cheng Lu
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Publication number: 20230093717Abstract: In an embodiment, a method includes: forming a fin extending from a substrate; forming a first gate mask over the fin, the first gate mask having a first width; forming a second gate mask over the fin, the second gate mask having a second width, the second width being greater than the first width; depositing a first filling layer over the first gate mask and the second gate mask; depositing a second filling layer over the first filling layer; planarizing the second filling layer with a chemical mechanical polish (CMP) process, the CMP process being performed until the first filling layer is exposed; and planarizing the first filling layer and remaining portions of the second filling layer with an etch-back process, the etch-back process etching materials of the first filling layer, the second filling layer, the first gate mask, and the second gate mask at the same rate.Type: ApplicationFiled: November 28, 2022Publication date: March 23, 2023Inventors: Shu-Wei Hsu, Yu-Jen Shen, Hao-Yun Cheng, Chih-Wei Wu, Ying-Tsung Chen, Ying-Ho Chen
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Patent number: 11515403Abstract: In an embodiment, a method includes: forming a fin extending from a substrate; forming a first gate mask over the fin, the first gate mask having a first width; forming a second gate mask over the fin, the second gate mask having a second width, the second width being greater than the first width; depositing a first filling layer over the first gate mask and the second gate mask; depositing a second filling layer over the first filling layer; planarizing the second filling layer with a chemical mechanical polish (CMP) process, the CMP process being performed until the first filling layer is exposed; and planarizing the first filling layer and remaining portions of the second filling layer with an etch-back process, the etch-back process etching materials of the first filling layer, the second filling layer, the first gate mask, and the second gate mask at the same rate.Type: GrantFiled: November 27, 2019Date of Patent: November 29, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shu-Wei Hsu, Yu-Jen Shen, Hao-Yun Cheng, Chih-Wei Wu, Ying-Tsung Chen, Ying-Ho Chen
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Publication number: 20210358816Abstract: Disclosed is a method of forming a semiconductor device. The method includes providing a precursor having a substrate and gate stacks over the substrate, wherein each of the gate stacks includes an electrode layer, a first hard mask (HM) layer over the electrode layer, and a second HM layer over the first HM layer. The method further includes depositing a dielectric layer over the substrate and the gate stacks and filling spaces between the gate stacks; and performing a first chemical mechanical planarization (CMP) process to partially remove the dielectric layer. The method further includes performing an etching process to remove the second HM layer and to partially remove the dielectric layer, thereby exposing the first HM layer. The method further includes performing a second CMP process to at least partially remove the first HM layer.Type: ApplicationFiled: July 30, 2021Publication date: November 18, 2021Inventors: Yu-Jen Shen, Ying-Ho Chen, Yung-Cheng Lu
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Patent number: 11081402Abstract: Disclosed is a method of forming a semiconductor device. The method includes providing a precursor having a substrate and gate stacks over the substrate, wherein each of the gate stacks includes an electrode layer, a first hard mask (HM) layer over the electrode layer, and a second HM layer over the first HM layer. The method further includes depositing a dielectric layer over the substrate and the gate stacks and filling spaces between the gate stacks; and performing a first chemical mechanical planarization (CMP) process to partially remove the dielectric layer. The method further includes performing an etching process to remove the second HM layer and to partially remove the dielectric layer, thereby exposing the first HM layer. The method further includes performing a second CMP process to at least partially remove the first HM layer.Type: GrantFiled: December 17, 2019Date of Patent: August 3, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Jen Shen, Ying-Ho Chen, Yung-Cheng Lu
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Publication number: 20210159325Abstract: In an embodiment, a method includes: forming a fin extending from a substrate; forming a first gate mask over the fin, the first gate mask having a first width; forming a second gate mask over the fin, the second gate mask having a second width, the second width being greater than the first width; depositing a first filling layer over the first gate mask and the second gate mask; depositing a second filling layer over the first filling layer; planarizing the second filling layer with a chemical mechanical polish (CMP) process, the CMP process being performed until the first filling layer is exposed; and planarizing the first filling layer and remaining portions of the second filling layer with an etch-back process, the etch-back process etching materials of the first filling layer, the second filling layer, the first gate mask, and the second gate mask at the same rate.Type: ApplicationFiled: November 27, 2019Publication date: May 27, 2021Inventors: Shu-Wei Hsu, Yu-Jen Shen, Hao-Yun Cheng, Chih-Wei Wu, Ying-Tsung Chen, Ying-Ho Chen
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Publication number: 20200118887Abstract: Disclosed is a method of forming a semiconductor device. The method includes providing a precursor having a substrate and gate stacks over the substrate, wherein each of the gate stacks includes an electrode layer, a first hard mask (HM) layer over the electrode layer, and a second HM layer over the first HM layer. The method further includes depositing a dielectric layer over the substrate and the gate stacks and filling spaces between the gate stacks; and performing a first chemical mechanical planarization (CMP) process to partially remove the dielectric layer. The method further includes performing an etching process to remove the second HM layer and to partially remove the dielectric layer, thereby exposing the first HM layer. The method further includes performing a second CMP process to at least partially remove the first HM layer.Type: ApplicationFiled: December 17, 2019Publication date: April 16, 2020Inventors: Yu-Jen Shen, Ying-Ho Chen, Yung-Cheng Lu
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Patent number: 10515860Abstract: Disclosed is a method of forming a semiconductor device. The method includes providing a precursor having a substrate and gate stacks over the substrate, wherein each of the gate stacks includes an electrode layer, a first hard mask (HM) layer over the electrode layer, and a second HM layer over the first HM layer. The method further includes depositing a dielectric layer over the substrate and the gate stacks and filling spaces between the gate stacks; and performing a first chemical mechanical planarization (CMP) process to partially remove the dielectric layer. The method further includes performing an etching process to remove the second HM layer and to partially remove the dielectric layer, thereby exposing the first HM layer. The method further includes performing a second CMP process to at least partially remove the first HM layer.Type: GrantFiled: March 8, 2018Date of Patent: December 24, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Jen Shen, Ying-Ho Chen, Yung-Cheng Lu
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Patent number: 10068992Abstract: A semiconductor device includes a fin structure for a fin field effect transistor (FET). The fin structure includes a base layer protruding from a substrate, an intermediate layer disposed over the base layer and an upper layer disposed over the intermediate layer. The fin structure further includes a first protective layer and a second protective layer made of a different material than the first protective layer. The intermediate layer includes a first semiconductor layer disposed over the base layer, the first protective layer covers at least side walls of the first semiconductor layer and the second protective layer covers at least side walls of the first protective layer.Type: GrantFiled: May 9, 2017Date of Patent: September 4, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hung Lo, Tzu-Hsiang Hsu, Chia-Jung Hsu, Feng-Cheng Yang, Teng-Chun Tsai, Ying-Ho Chen
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Publication number: 20180197795Abstract: Disclosed is a method of forming a semiconductor device. The method includes providing a precursor having a substrate and gate stacks over the substrate, wherein each of the gate stacks includes an electrode layer, a first hard mask (HM) layer over the electrode layer, and a second HM layer over the first HM layer. The method further includes depositing a dielectric layer over the substrate and the gate stacks and filling spaces between the gate stacks; and performing a first chemical mechanical planarization (CMP) process to partially remove the dielectric layer. The method further includes performing an etching process to remove the second HM layer and to partially remove the dielectric layer, thereby exposing the first HM layer. The method further includes performing a second CMP process to at least partially remove the first HM layer.Type: ApplicationFiled: March 8, 2018Publication date: July 12, 2018Inventors: Yu-Jen Shen, Ying-Ho Chen, Yung-Cheng Lu
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Patent number: 9917017Abstract: Disclosed is a method of forming a semiconductor device. The method includes providing a precursor having a substrate and gate stacks over the substrate, wherein each of the gate stacks includes an electrode layer, a first hard mask (HM) layer over the electrode layer, and a second HM layer over the first HM layer. The method further includes depositing a dielectric layer over the substrate and the gate stacks and filling spaces between the gate stacks; and performing a first chemical mechanical planarization (CMP) process to partially remove the dielectric layer. The method further includes performing an etching process to remove the second HM layer and to partially remove the dielectric layer, thereby exposing the first HM layer. The method further includes performing a second CMP process to at least partially remove the first HM layer.Type: GrantFiled: August 12, 2016Date of Patent: March 13, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Jen Shen, Ying-Ho Chen, Yung-Cheng Lu
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Publication number: 20170243957Abstract: A semiconductor device includes a fin structure for a fin field effect transistor (FET). The fin structure includes a base layer protruding from a substrate, an intermediate layer disposed over the base layer and an upper layer disposed over the intermediate layer. The fin structure further includes a first protective layer and a second protective layer made of a different material than the first protective layer. The intermediate layer includes a first semiconductor layer disposed over the base layer, the first protective layer covers at least side walls of the first semiconductor layer and the second protective layer covers at least side walls of the first protective layer.Type: ApplicationFiled: May 9, 2017Publication date: August 24, 2017Inventors: Hung LO, Tzu-Hsiang HSU, Chia-Jung HSU, Feng-Cheng YANG, Teng-Chun TSAI, Ying-Ho CHEN
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Publication number: 20170186650Abstract: Disclosed is a method of forming a semiconductor device. The method includes providing a precursor having a substrate and gate stacks over the substrate, wherein each of the gate stacks includes an electrode layer, a first hard mask (HM) layer over the electrode layer, and a second HM layer over the first HM layer. The method further includes depositing a dielectric layer over the substrate and the gate stacks and filling spaces between the gate stacks; and performing a first chemical mechanical planarization (CMP) process to partially remove the dielectric layer. The method further includes performing an etching process to remove the second HM layer and to partially remove the dielectric layer, thereby exposing the first HM layer. The method further includes performing a second CMP process to at least partially remove the first HM layer.Type: ApplicationFiled: August 12, 2016Publication date: June 29, 2017Inventors: Yu-Jen Shen, Ying-Ho Chen, Yung-Cheng Lu
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Patent number: 9680017Abstract: A semiconductor device includes a fin structure for a fin field effect transistor (FET). The fin structure includes a base layer protruding from a substrate, an intermediate layer disposed over the base layer and an upper layer disposed over the intermediate layer. The fin structure further includes a first protective layer and a second protective layer made of a different material than the first protective layer. The intermediate layer includes a first semiconductor layer disposed over the base layer, the first protective layer covers at least side walls of the first semiconductor layer and the second protective layer covers at least side walls of the first protective layer.Type: GrantFiled: September 16, 2015Date of Patent: June 13, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hung Lo, Chia-Jung Hsu, Teng-Chun Tsai, Tzu-Hsiang Hsu, Feng-Cheng Yang, Ying-Ho Chen
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Patent number: 9679782Abstract: A planarization method includes at least two steps. One of the steps is to implant at least one impurity into a wafer to form a polish stop layer in the wafer. The other one of the steps is to polish a top surface of the wafer until reaching the polish stop layer.Type: GrantFiled: January 7, 2016Date of Patent: June 13, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Ting Yen, Ying-Ho Chen
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Patent number: 9337066Abstract: The present disclosure relates to a wafer cleaning module for post CMP processes that reduces defects (e.g., watermarks, deposited particles) on a substrate, and an associated method. In some embodiments, the wafer cleaning module has a cleaning tank that may receive a semiconductor substrate within a cleaning medium. A pusher is may vertically move the semiconductor substrate from a starting position within the cleaning tank to an ending position. A position sensor may determine a position of the semiconductor substrate relative to a meniscus of the cleaning medium. Based upon the determined position, a control unit is may adjust a location of the starting position to a predetermined distance below the meniscus.Type: GrantFiled: November 5, 2013Date of Patent: May 10, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Ting Yen, Kao-Feng Liao, Ying-Ho Chen
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Publication number: 20150279686Abstract: One or more methods for semiconductor processing are provided. At least one of the methods include receiving information regarding a pre-etch back thickness of a first layer over a substrate, comparing the pre-etch back thickness to a desired thickness of the first layer, responsive to the pre-etch back thickness being greater than the desired thickness, determining parameters for an etch back process and performing the etch back process on the first layer to reduce the pre-etch back thickness to a first etch back thickness. The etch back process comprising performing a gas cluster ion beam etching process. In some embodiments, a second etch back process is performed. In some embodiments a wet clean process is performed on the first layer after the etch back process.Type: ApplicationFiled: March 31, 2014Publication date: October 1, 2015Inventors: Cheng-Yu Kuo, Teng-Chun Tsai, Ying-Ho Chen, Kuo-Min Lin, Ying-Tsung Chen, Bing-Hung Chen
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Publication number: 20150122291Abstract: The present disclosure relates to a wafer cleaning module for post CMP processes that reduces defects (e.g., watermarks, deposited particles) on a substrate, and an associated method. In some embodiments, the wafer cleaning module has a cleaning tank that may receive a semiconductor substrate within a cleaning medium. A pusher is may vertically move the semiconductor substrate from a starting position within the cleaning tank to an ending position. A position sensor may determine a position of the semiconductor substrate relative to a meniscus of the cleaning medium. Based upon the determined position, a control unit is may adjust a location of the starting position to a predetermined distance below the meniscus.Type: ApplicationFiled: November 5, 2013Publication date: May 7, 2015Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Ting Yen, Kao-Feng Liao, Ying-Ho Chen