Abstract: A static random access memory device is provided and includes a first gate of a first pass-gate transistor extending to cross a first number of fins in a first threshold voltage region of a substrate and a second gate of a second pass-gate transistor extending to cross a second number of fins in a second threshold voltage region of a substrate. A boundary of the first threshold voltage region between the first and second gates is arranged closer to one, which crosses a smaller number of fins, of the first and second gates.

Abstract: A static random access memory device includes a first gate of a write port circuit disposed in a standard threshold voltage region of a substrate and a second gate of a read port circuit disposed in a low threshold voltage region, abutting the standard threshold voltage region, of the substrate. A distance between a first edge, corresponding to an edge of the first gate, and a boundary, between the standard threshold voltage region and the low threshold voltage region, is different from a distance between the boundary and a second edge, corresponding to an edge of the second gate.

Abstract: A static random access memory device includes a first gate of a write port circuit disposed in a standard threshold voltage region of a substrate and a second gate of a read port circuit disposed in a low threshold voltage region, abutting the standard threshold voltage region, of the substrate. A distance between a first edge, corresponding to an edge of the first gate, and a boundary, between the standard threshold voltage region and the low threshold voltage region, is different from a distance between the boundary and a second edge, corresponding to an edge of the second gate.

Abstract: A static random access memory device includes a first gate, a second gate, and a third gate. The first gate extends in a first direction from a standard threshold voltage region of a substrate to a low threshold voltage region, abutting the standard threshold voltage region, of the substrate. The second gate is disposed in the standard threshold voltage region of the substrate. The third gate is disposed in the low threshold voltage region of the substrate. The standard threshold voltage region has a boundary at an edge of the second gate. The boundary extends in a second direction different from the first direction and is crossed by the first gate. A distance between the boundary and the first gate is different from a distance between the boundary and the second gate.

Abstract: A static random access memory device includes a first gate, a second gate, and a third gate. The first gate extends in a first direction from a standard threshold voltage region of a substrate to a low threshold voltage region, abutting the standard threshold voltage region, of the substrate. The second gate is disposed in the standard threshold voltage region of the substrate. The third gate is disposed in the low threshold voltage region of the substrate. The standard threshold voltage region has a boundary at an edge of the second gate. The boundary extends in a second direction different from the first direction and is crossed by the first gate. A distance between the boundary and the first gate is different from a distance between the boundary and the second gate.

Abstract: A semiconductor device includes: a first well having a first conductivity-type extending along a first direction; second and third wells having a second conductivity-type and disposed on opposite sides of the first well in a second direction; a first array of bitcells and a second array of bitcells disposed on the first to third wells; a strap cell disposed on the first to third wells and between the first and second arrays and including first and second well pickup regions having the first conductivity-type, disposed on the first well, and spaced-apart from each other in the first direction, and third and fourth well pickup regions having the second conductivity-type and disposed on the second and third wells, respectively; first and second conductive patterns electrically connected to the first and second well pickup regions, respectively; and a third conductive pattern electrically connected to the third and fourth well pickup regions.

Abstract: A static random access memory device includes a write circuit, a read port circuit, and a substrate. The write port circuit includes a first inverter, a second inverter cross-coupled with the first inverter, a first pass-gate transistor coupled to the first inverter, and a second pass-gate transistor coupled to the second inverter. The read port circuit includes a read pull-down transistor and a read pass-gate transistor that are coupled in series to each other. The substrate includes a standard threshold voltage (STV) region and a low threshold voltage (LVT) region abutting the STV region. The write port circuit is formed within the STV region, and the read port circuit is formed within the LVT region. The LVT region has a first boundary at an edge of a gate of the first pass-gate transistor, or approaching the edge of the gate of the first pass-gate transistor.

Abstract: A semiconductor device includes: a first well having a first conductivity-type extending along a first direction; second and third wells having a second conductivity-type and disposed on opposite sides of the first well in a second direction; a first array of bitcells and a second array of bitcells disposed on the first to third wells; a strap cell disposed on the first to third wells and between the first and second arrays and including first and second well pickup regions having the first conductivity-type, disposed on the first well, and spaced-apart from each other in the first direction, and third and fourth well pickup regions having the second conductivity-type and disposed on the second and third wells, respectively; first and second conductive patterns electrically connected to the first and second well pickup regions, respectively; and a third conductive pattern electrically connected to the third and fourth well pickup regions.

Abstract: A semiconductor device includes: a first well having a first conductivity-type extending along a first direction; second and third wells having a second conductivity-type and disposed on opposite sides of the first well in a second direction; a first array of bitcells and a second array of bitcells disposed on the first to third wells; a strap cell disposed on the first to third wells and between the first and second arrays and including first and second well pickup regions having the first conductivity-type, disposed on the first well, and spaced-apart from each other in the first direction, and third and fourth well pickup regions having the second conductivity-type and disposed on the second and third wells, respectively; first and second conductive patterns electrically connected to the first and second well pickup regions, respectively; and a third conductive pattern electrically connected to the third and fourth well pickup regions.

Abstract: A static random access memory device includes a write circuit, a read port circuit, and a substrate. The write port circuit includes a first inverter, a second inverter cross-coupled with the first inverter, a first pass-gate transistor coupled to the first inverter, and a second pass-gate transistor coupled to the second inverter. The read port circuit includes a read pull-down transistor and a read pass-gate transistor that are coupled in series to each other. The substrate includes a standard threshold voltage (STV) region and a low threshold voltage (LVT) region abutting the STV region. The write port circuit is formed within the STV region, and the read port circuit is formed within the LVT region. The LVT region has a first boundary at an edge of a gate of the first pass-gate transistor, or approaching the edge of the gate of the first pass-gate transistor.

Abstract: A semiconductor device includes: a first well having a first conductivity-type extending along a first direction; second and third wells having a second conductivity-type and disposed on opposite sides of the first well in a second direction; a first array of bitcells and a second array of bitcells disposed on the first to third wells; a strap cell disposed on the first to third wells and between the first and second arrays and including first and second well pickup regions having the first conductivity-type, disposed on the first well, and spaced-apart from each other in the first direction, and third and fourth well pickup regions having the second conductivity-type and disposed on the second and third wells, respectively; first and second conductive patterns electrically connected to the first and second well pickup regions, respectively; and a third conductive pattern electrically connected to the third and fourth well pickup regions.