Patents by Inventor Ying-Jui Huang

Ying-Jui Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8823166
    Abstract: Apparatus and methods for providing solder pillar bumps. Pillar bump connections are formed on input/output terminals for integrated circuits by forming a pillar of conductive material using plating of a conductive material over terminals of an integrated circuit. A base portion of the pillar bump has a greater width than an upper portion. A cross-section of the base portion of the pillar bump may make a trapezoidal, rectangular or sloping shape. Solder material may be formed on the top surface of the pillar. The resulting solder pillar bumps form fine pitch package solder connections that are more reliable than those of the prior art.
    Type: Grant
    Filed: August 30, 2010
    Date of Patent: September 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chung Lin, Chung-Shi Liu, Meng-Wei Chou, Kuo Cheng Lin, Wen-Hsiung Lu, Chien Ling Hwang, Ying-Jui Huang, De-Yuan Lu
  • Publication number: 20140048586
    Abstract: The present disclosure is directed to an apparatus for the application of soldering flux to a semiconductor workpiece. In some embodiments the apparatus comprises a dipping plate having a reservoir which is adapted to containing different depths of flux material. In some embodiments, the reservoir comprises at least two landing regions having sidewalls which form first and second dipping zones. The disclosed apparatus can allow dipping of the semiconductor workpiece in different depths of soldering flux without the necessity for changing dipping plates.
    Type: Application
    Filed: August 15, 2012
    Publication date: February 20, 2014
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Bor-Ping Jang, Lin-Wei Wang, Ying-Jui Huang, Yi-Li Hsiao, Chien Ling Hwang, Chung-Shi Liu
  • Publication number: 20140030849
    Abstract: An apparatus includes a guide ring, and a bond head installed on the guide ring. The bond head is configured to move in loops along the guide ring.
    Type: Application
    Filed: September 27, 2013
    Publication date: January 30, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien Ling Hwang, Ying-Jui Huang, Yi-Li Hsiao
  • Patent number: 8546802
    Abstract: An apparatus includes a guide ring, and a bond head installed on the guide ring. The bond head is configured to move in loops along the guide ring. The bond head is configured to pick up dies and place the dies during the loops.
    Type: Grant
    Filed: November 7, 2011
    Date of Patent: October 1, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien Ling Hwang, Ying-Jui Huang, Yi-Li Hsiao
  • Publication number: 20130146647
    Abstract: A method includes reflowing a solder region of a package structure, and performing a cleaning on the package structure at a cleaning temperature higher than a room temperature. Between the step of reflowing and the step of cleaning, the package structure is not cooled to temperatures close to the room temperature.
    Type: Application
    Filed: December 7, 2011
    Publication date: June 13, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Shi Liu, Chien Ling Hwang, Bor-Ping Jang, Ying-Jui Huang
  • Publication number: 20130115752
    Abstract: An apparatus includes a guide ring, and a bond head installed on the guide ring. The bond head is configured to move in loops along the guide ring.
    Type: Application
    Filed: November 7, 2011
    Publication date: May 9, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien Ling Hwang, Ying-Jui Huang, Yi-Li Hsiao
  • Patent number: 8317077
    Abstract: A method of bonding includes providing a first work piece, and attaching a second work piece on the first work piece, with a solder bump disposed between the first and the second work pieces. The second work piece is heated using a heating head of a heating tool to melt the solder bump. After the step of heating the second work piece, one of the first and the second work pieces is allowed to move freely in a horizontal direction to self-align the first and the second work pieces. After the step of allowing one of the first and the second work pieces to move, a temperature of the heating head is lowed until the first solder bump solidifies to form a second solder bump.
    Type: Grant
    Filed: January 16, 2012
    Date of Patent: November 27, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien Ling Hwang, Ying-Jui Huang, Cheng-Chung Lin, Chung-Shi Liu
  • Publication number: 20120227886
    Abstract: A portable electrostatic chuck carrier includes a holder having a dielectric top surface, and bipolar electrodes under the dielectric top surface. The bipolar electrodes includes positive electrodes and negative electrodes electrically insulated from the positive electrodes. The positive electrodes and the negative electrodes are allocated in an alternating pattern in a plane substantially parallel to the dielectric top surface.
    Type: Application
    Filed: March 10, 2011
    Publication date: September 13, 2012
    Applicant: Taipei Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Li Hsiao, Chen-Hua Yu, Chung-Shi Liu, Chien Ling Hwang, Ying-Jui Huang
  • Patent number: 8258055
    Abstract: An embodiment of the disclosure includes a conductive bump on a semiconductor die. A substrate is provided. A bond pad is over the substrate. An under bump metallurgy (UBM) layer is over the bond pad. A copper pillar is over the UBM layer. The copper pillar has a top surface with a first width and sidewalls with a concave shape. A nickel layer having a top surface and a bottom surface is over the top surface of the copper pillar. The bottom surface of the nickel layer has a second width. A ratio of the second width to the first width is between about 0.93 to about 1.07. A solder material is over the top surface of the cap layer.
    Type: Grant
    Filed: July 8, 2010
    Date of Patent: September 4, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien Ling Hwang, Ying-Jui Huang, Zheng-Yi Lim, Yi-Yang Lei, Cheng-Chung Lin, Chung-Shi Liu
  • Patent number: 8177862
    Abstract: A method includes allowing a work piece having a solder bump to contact a bond head; heating the bond head until the solder bump is melted; and conducting a cooling media into the bond head to cool the solder bump and to solidify the solder bump.
    Type: Grant
    Filed: October 8, 2010
    Date of Patent: May 15, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Chien Ling Hwang, Cheng-Chung Lin, Ying-Jui Huang, Chung-Shi Liu
  • Publication number: 20120111922
    Abstract: A method of bonding includes providing a first work piece, and attaching a second work piece on the first work piece, with a solder bump disposed between the first and the second work pieces. The second work piece is heated using a heating head of a heating tool to melt the solder bump. After the step of heating the second work piece, one of the first and the second work pieces is allowed to move freely in a horizontal direction to self-align the first and the second work pieces. After the step of allowing one of the first and the second work pieces to move, a temperature of the heating head is lowed until the first solder bump solidifies to form a second solder bump.
    Type: Application
    Filed: January 16, 2012
    Publication date: May 10, 2012
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien Ling Hwang, Ying-Jui Huang, Cheng-Chung Lin, Chung-Shi Liu
  • Publication number: 20120088362
    Abstract: A method includes allowing a work piece having a solder bump to contact a bond head; heating the bond head until the solder bump is melted; and conducting a cooling media into the bond head to cool the solder bump and to solidify the solder bump.
    Type: Application
    Filed: October 8, 2010
    Publication date: April 12, 2012
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien Ling Hwang, Cheng-Chung Lin, Ying-Jui Huang, Chung-Shi Liu
  • Publication number: 20120049346
    Abstract: Apparatus and methods for providing solder pillar bumps. Pillar bump connections are formed on input/output terminals for integrated circuits by forming a pillar of conductive material using plating of a conductive material over terminals of an integrated circuit. A base portion of the pillar bump has a greater width than an upper portion. A cross-section of the base portion of the pillar bump may make a trapezoidal, rectangular or sloping shape. Solder material may be formed on the top surface of the pillar. The resulting solder pillar bumps form fine pitch package solder connections that are more reliable than those of the prior art.
    Type: Application
    Filed: August 30, 2010
    Publication date: March 1, 2012
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chung Lin, Chung-Shi Liu, Meng-Wei Chou, Kuo Cheng Lin, Wen-Hsiung Lu, Chien Ling Hwang, Ying-Jui Huang, De-Yuan Lu
  • Patent number: 8104666
    Abstract: A method of bonding includes providing a first work piece, and attaching a second work piece on the first work piece, with a solder bump disposed between the first and the second work pieces. The second work piece is heated using a heating head of a heating tool to melt the solder bump. After the step of heating the second work piece, one of the first and the second work pieces is allowed to move freely in a horizontal direction to self-align the first and the second work pieces. After the step of allowing one of the first and the second work pieces to move, a temperature of the heating head is lowed until the first solder bump solidifies to form a second solder bump.
    Type: Grant
    Filed: September 1, 2010
    Date of Patent: January 31, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien Ling Hwang, Ying-Jui Huang, Cheng-Chung Lin, Chung-Shi Liu
  • Publication number: 20120007230
    Abstract: An embodiment of the disclosure includes a conductive bump on a semiconductor die. A substrate is provided. A bond pad is over the substrate. An under bump metallurgy (UBM) layer is over the bond pad. A copper pillar is over the UBM layer. The copper pillar has a top surface with a first width and sidewalls with a concave shape. A nickel layer having a top surface and a bottom surface is over the top surface of the copper pillar. The bottom surface of the nickel layer has a second width. A ratio of the second width to the first width is between about 0.93 to about 1.07. A solder material is over the top surface of the cap layer.
    Type: Application
    Filed: July 8, 2010
    Publication date: January 12, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien Ling Hwang, Ying-Jui Huang, Zheng-Yi Lim, Yi-Yang Lei, Cheng-Chung Lin, Chung-Shi Liu
  • Patent number: 8088692
    Abstract: A method for fabricating a multilayer microstructure with balancing residual stress capability includes forming a multilayer microstructure on a silicon substrate and conducting a step of isotropic plasma etching. The multilayer microstructure includes a first metal layer and a second metal layer patterned and aligned symmetrically to form etching through holes; a metal via layer surrounding each etching through hole; and an insulating layer filling each etching through hole and disposed between the substrate and the first metal layer. The step of isotropic chemical plasma etching removes the insulating layer in each etching through hole, the insulating layer between the substrate and the metal layer and a portion of the substrate to form a suspended multilayer microstructure on the substrate, during which a chamber pressure larger than vacuum and maintains a ratio between a lateral etching rate and a vertical etching rate between 0.
    Type: Grant
    Filed: October 8, 2009
    Date of Patent: January 3, 2012
    Assignee: National Tsing Hua University
    Inventors: Ying-Jui Huang, Hwai-Pwu Chou
  • Publication number: 20110008962
    Abstract: A method for fabricating a multilayer microstructure with balancing residual stress capability includes forming a multilayer microstructure on a substrate and conducting a step of isotropic plasma etching. The multilayer microstructure includes a first metal layer, a second metal layer, a metal via layer and an insulating layer. The first metal layer and the second metal layer are patterned and aligned symmetrically so as to form etching through holes. The metal via layer surrounds each etching through hole. The insulating layer fills each etching through hole and is disposed between the substrate and the first metal layer. The step of isotropic chemical plasma etching removes the insulating layer in each etching through hole and the insulating layer between the substrate and the metal layer so as to form a suspended multilayer microstructure on the substrate.
    Type: Application
    Filed: October 8, 2009
    Publication date: January 13, 2011
    Inventors: Ying-Jui HUANG, Hwai-Pwu CHOU
  • Publication number: 20100165316
    Abstract: An inclined exposure lithography system is disclosed, which comprises: a substrate; a photoresist layer, formed on the substrate; a mask, disposed over the photoresist layer with a gap therebetween; and a refraction element disposed over the mask so that a light beam from a light source is refracted by a specific angle.
    Type: Application
    Filed: March 10, 2010
    Publication date: July 1, 2010
    Applicant: Industrial Technology Research Institute
    Inventors: YING-JUI HUANG, Cheng-Hsuan Lin, Fuh-Yu Chang
  • Publication number: 20090161117
    Abstract: A method and an apparatus are disclosed for scatterfield microscopical measurement. The method integrates a scatterometer and a bright-field microscope for enabling the measurement precision to be better than the optical diffraction limit. With the aforesaid method and apparatus, a detection beam is generated by performing a process on a uniform light using an LCoS (liquid crystal on silicon) or a DMD (digital micro-mirror device) which is to directed to image on the back focal plane of an object to be measured, and then scattered beams resulting from the detection beam on the object's surface are focused on a plane to form an optical signal which is to be detected by an array-type detection device. The detection beam can be oriented by the modulation device to illuminate on the object at a number of different angles, by which zero order or higher order diffraction intensities at different positions of the plane at different incident angles can be collected.
    Type: Application
    Filed: October 15, 2008
    Publication date: June 25, 2009
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: YING-JUI HUANG, CHENG-HSUAN LIN, FUH-YU CHANG