Patents by Inventor Ying-te Ou
Ying-te Ou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11806710Abstract: A semiconductor package structure includes a substrate, a die and a conductive structure. The die is disposed on or within the substrate. The die has a first surface facing away from the substrate and includes a sensing region and a pad at the first surface of the die. The first surface of the die has a first edge and a second edge opposite to the first edge. The sensing region is disposed adjacent to the first edge. The pad is disposed away from the first edge. The conductive structure electrically connects the pad and the substrate. The sensing region has a first end distal to the first edge of the first surface of the die. A distance from the first end of the sensing region to a center of the pad is equal to or greater than a distance from the first end of the sensing region to the first edge of the first surface of the die.Type: GrantFiled: June 4, 2020Date of Patent: November 7, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Hsiao-Yen Lee, Ying-Te Ou, Chin-Cheng Kuo, Chung Hao Chen
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Publication number: 20210379590Abstract: A semiconductor package structure includes a substrate, a die and a conductive structure. The die is disposed on or within the substrate. The die has a first surface facing away from the substrate and includes a sensing region and a pad at the first surface of the die. The first surface of the die has a first edge and a second edge opposite to the first edge. The sensing region is disposed adjacent to the first edge. The pad is disposed away from the first edge. The conductive structure electrically connects the pad and the substrate. The sensing region has a first end distal to the first edge of the first surface of the die. A distance from the first end of the sensing region to a center of the pad is equal to or greater than a distance from the first end of the sensing region to the first edge of the first surface of the die.Type: ApplicationFiled: June 4, 2020Publication date: December 9, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Hsiao-Yen LEE, Ying-Te OU, Chin-Cheng KUO, Chung Hao CHEN
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Patent number: 10600759Abstract: In one or more embodiments, a semiconductor device includes a substrate, a first dielectric layer and a first conductive layer. The substrate includes a first surface and a second surface opposite the first surface. The first dielectric layer is on the first surface of the substrate. The first conductive layer is on the first surface of the substrate and includes a first portion on the first dielectric layer and a second portion surrounded by the first dielectric layer. The second portion of the first conductive layer extends from the first portion of the first conductive layer through the first dielectric layer to contact the first surface of the substrate.Type: GrantFiled: January 11, 2017Date of Patent: March 24, 2020Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chih-Pin Hung, Ying-Te Ou, Pao-Nan Lee
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Patent number: 10236208Abstract: The present disclosure relates to a semiconductor package structure and a method of manufacturing the same. The semiconductor package structure includes a semiconductor substrate having a first surface and a second surface opposite the first surface. The semiconductor substrate has a space extending from the second surface to the first surface and an insulation body is disposed in the space. The semiconductor package structure includes conductive posts in the insulation body.Type: GrantFiled: June 16, 2016Date of Patent: March 19, 2019Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chin-Cheng Kuo, Pao-Nan Lee, Chih-Pin Hung, Ying-Te Ou
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Publication number: 20170365515Abstract: The present disclosure relates to a semiconductor package structure and a method of manufacturing the same. The semiconductor package structure includes a semiconductor substrate having a first surface and a second surface opposite the first surface. The semiconductor substrate has a space extending from the second surface to the first surface and an insulation body is disposed in the space. The semiconductor package structure includes conductive posts in the insulation body.Type: ApplicationFiled: June 16, 2016Publication date: December 21, 2017Inventors: Chin-Cheng KUO, Pao-Nan LEE, Chih-Pin HUNG, Ying-Te OU
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Publication number: 20170287863Abstract: A semiconductor die includes a semiconductor body, an insulating layer, a conductive circuit layer and at least one conductive bump. The semiconductor body has a first surface, a second surface and a side surface extending between the first surface and the second surface. The insulating layer is disposed on the first surface and the side surface of the semiconductor body. The insulating layer includes a first insulating layer over the semiconductor body and a second insulating layer over the first insulating later. The insulating layer includes a step structure. The conductive circuit layer is electrically connected to the first surface of the semiconductor body, the conductive circuit layer includes at least one pad, and the conductive bump is electrically connected to the pad.Type: ApplicationFiled: June 20, 2017Publication date: October 5, 2017Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chin-Cheng KUO, Ying-Te OU, Lu-Ming LAI
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Patent number: 9768103Abstract: An embedded chip substrate includes a first insulation layer, a core layer, a chip, a second insulation layer, a first circuit layer, and a second circuit layer. The core layer disposed on the first insulation layer has an opening that exposes a portion of the first insulation layer. The chip is adhered into a recess constructed by the opening and the first insulation layer. The second insulation layer is disposed on the core layer for covering the chip. The first circuit layer is disposed at the outer side of the first insulation layer located between the first circuit layer and the core layer. The second circuit layer is disposed at the outer side of the second insulation layer located between the second circuit layer and the core layer. The first circuit layer is electrically connected to the second circuit layer that is electrically connected to the chip.Type: GrantFiled: January 7, 2016Date of Patent: September 19, 2017Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Yung-Hui Wang, Ying-Te Ou
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Patent number: 9728451Abstract: The present invention provides a semiconductor wafer, a semiconductor chip and a semiconductor package. The semiconductor wafer includes a first pad, a first inter-layer dielectric and a second pad. The first pad is disposed on a top surface of a semiconductor substrate and has a solid portion and a plurality of through holes. The first inter-layer dielectric covers the first pad. The second pad is disposed on the first inter-layer dielectric and has a solid portion and a plurality of through holes, wherein the through holes of the first pad correspond to the solid portion of the second pad.Type: GrantFiled: August 21, 2014Date of Patent: August 8, 2017Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chen-Chao Wang, Ying-Te Ou
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Patent number: 9711473Abstract: A semiconductor die includes a semiconductor body, an insulating layer, a conductive circuit layer and at least one conductive bump. The semiconductor body has a first surface, a second surface and a side surface extending between the first surface and the second surface. The insulating layer is disposed on the first surface and the side surface of the semiconductor body. The insulating layer includes a first insulating layer over the semiconductor body and a second insulating layer over the first insulating later. The insulating layer includes a step structure. The conductive circuit layer is electrically connected to the first surface of the semiconductor body, the conductive circuit layer includes at least one pad, and the conductive bump is electrically connected to the pad.Type: GrantFiled: February 26, 2016Date of Patent: July 18, 2017Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chin-Cheng Kuo, Ying-Te Ou, Lu-Ming Lai
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Publication number: 20170200702Abstract: In one or more embodiments, a semiconductor device includes a substrate, a first dielectric layer and a first conductive layer. The substrate includes a first surface and a second surface opposite the first surface. The first dielectric layer is on the first surface of the substrate. The first conductive layer is on the first surface of the substrate and includes a first portion on the first dielectric layer and a second portion surrounded by the first dielectric layer. The second portion of the first conductive layer extends from the first portion of the first conductive layer through the first dielectric layer to contact the first surface of the substrate.Type: ApplicationFiled: January 11, 2017Publication date: July 13, 2017Inventors: Chih-Pin HUNG, Ying-Te OU, Pao-Nan LEE
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Publication number: 20160118325Abstract: An embedded chip substrate includes a first insulation layer, a core layer, a chip, a second insulation layer, a first circuit layer, and a second circuit layer. The core layer disposed on the first insulation layer has an opening that exposes a portion of the first insulation layer. The chip is adhered into a recess constructed by the opening and the first insulation layer. The second insulation layer is disposed on the core layer for covering the chip. The first circuit layer is disposed at the outer side of the first insulation layer located between the first circuit layer and the core layer. The second circuit layer is disposed at the outer side of the second insulation layer located between the second circuit layer and the core layer. The first circuit layer is electrically connected to the second circuit layer that is electrically connected to the chip.Type: ApplicationFiled: January 7, 2016Publication date: April 28, 2016Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Yung-Hui WANG, Ying-Te OU
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Patent number: 9253887Abstract: An embedded chip substrate includes a first insulation layer, a core layer, a chip, a second insulation layer, a first circuit layer, and a second circuit layer. The core layer disposed on the first insulation layer has an opening that exposes a portion of the first insulation layer. The chip is adhered into a recess constructed by the opening and the first insulation layer. The second insulation layer is disposed on the core layer for covering the chip. The first circuit layer is disposed at the outer side of the first insulation layer located between the first circuit layer and the core layer. The second circuit layer is disposed at the outer side of the second insulation layer located between the second circuit layer and the core layer. The first circuit layer is electrically connected to the second circuit layer that is electrically connected to the chip.Type: GrantFiled: August 1, 2012Date of Patent: February 2, 2016Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Yung-Hui Wang, Ying-Te Ou
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Patent number: 8963316Abstract: The present invention relates to a semiconductor device and a method for making the same. The semiconductor device includes a substrate, a first redistribution layer and a conductive via. The substrate has a substrate body and a pad. The pad and the first redistribution layer are disposed adjacent to the first surface of the substrate body, and electrically connected to each other. The interconnection metal is disposed in a through hole of the substrate body, and contacts the first redistribution layer. Whereby, the pad can be electrically connected to the second surface of the substrate body through the first redistribution layer and the conductive via.Type: GrantFiled: February 15, 2012Date of Patent: February 24, 2015Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Chih-Jing Hsu, Ying-Te Ou, Chieh-Chen Fu, Che-Hau Huang
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Patent number: 8937387Abstract: The disclosure concerns a semiconductor device having conductive vias. In an embodiment, the semiconductor device includes a substrate having at least one conductive via formed therein. The conductive via has a first end substantially coplanar with an inactive surface of the substrate. A circuit layer is disposed adjacent to an active surface of the substrate and electrically connected to a second end of the conductive via. A redistribution layer is disposed adjacent to the inactive surface of the substrate, the redistribution layer having a first portion disposed on the first end an electrically connected thereto, and a second portion positioned upward and away from the first portion. A die is disposed adjacent to the inactive surface of the substrate and electrically connected to the second portion of the redistribution layer.Type: GrantFiled: November 7, 2012Date of Patent: January 20, 2015Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Che-Hau Huang, Ying-Te Ou
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Publication number: 20140363967Abstract: The present invention provides a semiconductor wafer, a semiconductor chip and a semiconductor package. The semiconductor wafer includes a first pad, a first inter-layer dielectric and a second pad. The first pad is disposed on a top surface of a semiconductor substrate and has a solid portion and a plurality of through holes. The first inter-layer dielectric covers the first pad. The second pad is disposed on the first inter-layer dielectric and has a solid portion and a plurality of through holes, wherein the through holes of the first pad correspond to the solid portion of the second pad.Type: ApplicationFiled: August 21, 2014Publication date: December 11, 2014Inventors: Chen-Chao Wang, Ying-Te Ou
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Patent number: 8841751Abstract: The present invention provides a semiconductor wafer, a semiconductor chip and a semiconductor package. The semiconductor wafer includes a first pad, a first inter-layer dielectric and a second pad. The first pad is disposed on a top surface of a semiconductor substrate and has a solid portion and a plurality of through holes. The first inter-layer dielectric covers the first pad. The second pad is disposed on the first inter-layer dielectric and has a solid portion and a plurality of through holes, wherein the through holes of the first pad correspond to the solid portion of the second pad.Type: GrantFiled: January 23, 2013Date of Patent: September 23, 2014Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Chen-Chao Wang, Ying-Te Ou
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Publication number: 20140203412Abstract: The present invention provides a semiconductor wafer, a semiconductor chip and a semiconductor package. The semiconductor wafer includes a first pad, a first inter-layer dielectric and a second pad. The first pad is disposed on a top surface of a semiconductor substrate and has a solid portion and a plurality of through holes. The first inter-layer dielectric covers the first pad. The second pad is disposed on the first inter-layer dielectric and has a solid portion and a plurality of through holes, wherein the through holes of the first pad correspond to the solid portion of the second pad.Type: ApplicationFiled: January 23, 2013Publication date: July 24, 2014Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chen-Chao Wang, Ying-Te Ou
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Publication number: 20140124919Abstract: The present invention relates to a semiconductor device and semiconductor process. The semiconductor device includes a substrate, a circuit layer, a plurality of under bump metallurgies (UBMs), a redistribution layer and a plurality of interconnection metals. The substrate has an active surface and a inactive surface. The circuit layer and the under bump metallurgies (UBMs) are disposed adjacent to the active surface. The redistribution layer is disposed adjacent to the inactive surface. The interconnection metals electrically connect the circuit layer and redistribution layer.Type: ApplicationFiled: November 7, 2012Publication date: May 8, 2014Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Che-Hau Huang, Ying-Te Ou
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Patent number: 8653634Abstract: A wafer level package including a shield connected to a plurality of conductive elements disposed on a silicon wafer. The conductive elements are arranged to individually enclose micro-structure elements located on the silicon wafer within cavities formed by the conductive elements for better shielding performance. The shield and the conductive elements function as the EMI shield.Type: GrantFiled: June 11, 2012Date of Patent: February 18, 2014Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Chi Tsung Chiu, Ying-Te Ou
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Publication number: 20130328176Abstract: A wafer level package including a shield connected to a plurality of conductive elements disposed on a silicon wafer. The conductive elements are arranged to individually enclose micro-structure elements located on the silicon wafer within cavities formed by the conductive elements for better shielding performance. The shield and the conductive elements function as the EMI shield.Type: ApplicationFiled: June 11, 2012Publication date: December 12, 2013Inventors: Chi Tsung Chiu, Ying-Te Ou