Abstract: An instruction simulation device and a method thereof are provided. The instruction simulation device includes a processor. The processor includes an instruction decoder which generates format information of a ready-for-execution instruction. The processor determines whether the ready-for-execution instruction currently executed by the processor is a compatible instruction or an extended instruction based on the format information of the ready-for-execution instruction. If the ready-for-execution instruction is an extended instruction under the new instruction set or the extended instruction set, the processor converts the ready-for-execution instruction into a simulation program corresponding to the extended instruction, and simulates an execution result of the ready-for-execution instruction by executing the simulation program. The simulation program is composed of at least one compatible instructions of the processor.

Abstract: A computer system with data encryption and decryption on system memory is shown. The computer system has a system memory storing data, and a processor coupled to the system memory. The processor has key registers storing multiple keys. Based on the access address on the system memory, the processor selects a target key from the key registers, to apply the target key to perform data encryption and decryption on the system memory.

Abstract: A computer system with a system memory encryption and decryption function is shown, which uses global context isolated keys to encrypt and decrypt data of a system memory that is coupled to the processor. In particular, the processor identifies the keys using key identification codes (KeyID), and each key identification code includes a global context identification code (GCID).

Abstract: A computer system with a processor having an encryption and decryption engine is shown. The encryption and decryption engine includes a key table, which is provided for encryption and decryption of the system memory. In response to a platform setting instruction, the processor reads a key identification code from a key identification code register, and reads control parameters from a control parameter register. Based on the control parameters, the processor manages a key, associated with the key identification code, in the key table.

Abstract: A processor with an elliptic curve cryptographic algorithm and a data processing method thereof are shown. Three elliptic curve cryptographic instructions are proposed in the instruction set architecture for key exchange between an initiator and a responder. The initiator device executes the first elliptic curve cryptographic instruction to generate a key pair (rA, RA). In addition to considering the first temporary public key RA, the responder device further takes the second temporary public key RB into consideration when executing the second elliptic curve cryptographic instruction to generate the responder-generated shared key KB. Based on the temporary private key rA, and the temporary public keys RA and RB, the initiator device executes the third elliptic curve cryptographic instruction to generate the initiator-generated shared key KA.

Abstract: A processor and a method for designating an in-core cache of a hierarchical cache system to perform writing-back and invalidation of cached data are shown. In response to an instruction that is in the instruction set architecture and is executed to designate a designated-level cache within the current core as a target to perform writing-back and invalidation, a decoder of the current core outputs microinstructions. According to the microinstructions, a level-designation request indicating the designated-level cache within the current core is transferred to the hierarchical cache system through the memory order buffer. In response to the level-designation request, the hierarchical cache system recognizes cache lines related to the designated-level cache of the current core, writes modified cache lines (which are obtained from the recognized cache lines) back to the system memory, and then invalidates all the recognized cache lines from the hierarchical cache system.

Abstract: A processor for building a homogeneous dual computing system is shown. The processor has a trusted core, a normal core, and a shared cache. The trusted core has an access right to an isolated storage space of a system memory. The normal core is homogeneous with the trusted core, and is prohibited from accessing the isolated storage space. In response to a cache flush instruction issued by the normal core, the trusted core initiates and executes a second cache write-back instruction that is different from the first cache write-back instruction. According to the second cache write-back instruction, isolated data associated with the isolated storage space and cached in the shared cache is written back to the isolated storage space before being flushed.

Abstract: A technology flushing a hierarchical cache structure based on a designated key identification code and a designated address. A processor includes a first core and a last level cache (LLC). The first core includes a decoder, a memory ordering buffer, and a first in-core cache module. In response to an Instruction Set Architecture (ISA) instruction that requests to flush a hierarchical cache structure according to a designated key identification code and a designated address, the decoder outputs at least one microinstruction. According to the at least one microinstruction, a flushing request with the designated key identification code and the designated address is provided to the first in-core cache module through the memory ordering buffer, and then the first in-core cache module provides the LLC with the flushing request, so that the LLC flushes its matching cache line which matches the designated key identification code and the designated address.

Abstract: A processor with a Hash cryptographic algorithm and a data processing method are shown. In response to one single Hash cryptographic instruction of an instruction set architecture, the processor reads a first storage space within a system memory to obtain an input message of a limited length, and processes the input message in accordance with the Hash cryptographic algorithm to generate a final Hash value of a specific length.

Abstract: A processor with a block cipher algorithm and a data encryption and decryption method operated by the processor are shown. The processor uses a register to store an input key pointer pointing to an input key. In response to one single block cipher instruction of an instruction set architecture (ISA), the processor obtains input data from a first system memory area, performs the block cipher algorithm on the input data based on the input key indicated by the input key pointer stored in the register to encrypt or decrypt the input data to generate output data, and stores the output data in a second system memory area, or an internal storage area within the processor.

Abstract: A processor with an elliptic curve cryptographic algorithm and a data processing method thereof are shown. Three elliptic curve cryptographic instructions are proposed in the instruction set architecture for key exchange between an initiator and a responder. The initiator device executes the first elliptic curve cryptographic instruction to generate a key pair (rA, RA). In addition to considering the first temporary public key RA, the responder device further takes the second temporary public key RB into consideration when executing the second elliptic curve cryptographic instruction to generate the responder-generated shared key KB. Based on the temporary private key rA, and the temporary public keys RA and RB, the initiator device executes the third elliptic curve cryptographic instruction to generate the initiator-generated shared key KA.

Abstract: A processor with an elliptic curve cryptographic algorithm and a data processing method thereof are shown. The processor has a first register, storing a private key pointer pointing to a private key. In response to a single elliptic curve cryptographic instruction of an instruction set architecture, the processor reads a ciphertext input from a first storage space within a system memory, performing a decryption procedure using the elliptic curve cryptographic algorithm on the ciphertext input based on the private key obtained by referring to the first register to decrypt the ciphertext input and generate a plaintext output, and programming the plaintext output into a second storage space within the system memory.

Abstract: A processor with an elliptic curve cryptographic algorithm and a data processing method thereof are shown. The processor has a first register storing a Hash value pointer, a second register storing a public key pointer, a third register storing a signature pointer, and a fourth register for storage of a verified result. In response to a first elliptic curve cryptographic instruction of an instruction set architecture, the processor reads the Hash value of the data by referring to the first register, obtains the public key by referring to the second register, obtains the digital signature to be verified by referring to the third register, performs a signature verification procedure using the elliptic curve cryptographic algorithm on the Hash value based on the public key and the digital signature to be verified to generate the verified result, and programs the verified result into the fourth register.

Abstract: A computing system with a first instruction of an instruction set architecture (ISA) for direct invalidation, without writing back, in a hierarchical cache structure based on one single designated key identification code, and a second instruction of ISA for direct invalidation, without writing back, in the hierarchical cache structure based on a plurality of designated key identification codes is shown. A decoder transforms the first or second instruction into at least one microinstruction. Based on the at least one microinstruction, one direct invalidation request is provided corresponding to each designated key identification code, to be passed to the hierarchical cache structure through a memory ordering buffer. For each direct invalidation request, the cache line write-back and invalidation regarding a designated key identification code is performed on a last-level cache first, and then is performed on the in-core cache modules.

Abstract: A processor and a method for designating a demotion target to demote the demotion target from an in-core cache structure to an out-of-core cache structure is shown. In response to a cache data demotion instruction supported by an instruction set architecture, a first core of a processor operates a decoder to decode the cache data demotion instruction into microinstructions. According to the microinstructions, a demotion target designation request is transferred to a last-level cache (LLC) through a memory order buffer to drive the LLC to query an out-of-core cache table. According to the demotion target's cache status in the first core obtained from the out-of-core cache table, the LLC outputs a snoop request to the first core to snoop on the demotion target and demote the demotion target from the in-core cache structure of the first core to the LLC.

Abstract: An instruction execution method for a microprocessor is provided. The microprocessor includes a model specific register (MSR). And, the instruction execution method includes the following steps. A target instruction is received using an instruction cache. The target instruction is decoded using an instruction translator to determine whether the target instruction is a specific instruction is a specific instruction. When the target instruction is the specific instruction, a model specific register index of the target instruction is obtained to directly read or write the model specific register.

Abstract: A processor with protection of an isolated memory and protection method for the isolated memory accessible only by a trusted core are shown. A processor has a trusted core with a right to access an isolated memory planned on a system memory, a normal core prohibited from accessing the isolated memory, and a last-level cache shared by the trusted core and the normal core. The in-core cache structure of the normal core and the last-level cache are included in a hierarchical cache system. In response to a memory access request issued by the normal core, the hierarchical cache system determines whether the memory access request hits the isolated memory and, if yes, the hierarchical cache system rejects the memory access request.

Abstract: An instruction configuration and execution method includes the following steps. A target instruction is received through an instruction cache. The target instruction is decoded by an instruction translator. It is determined whether the target instruction has the authority to read or write the model specific register in an unprivileged state. It is determined whether the model specific register index of the specific instruction corresponds to a specific model specific register, so as to order the microprocessor to perform an instruction serialization operation.

Abstract: A processor for building a homogeneous dual computing system is shown. The processor has a trusted core, a normal core, and a shared cache. The trusted core has an access right to an isolated storage space of a system memory. The normal core is homogeneous with the trusted core, and is prohibited from accessing the isolated storage space. In response to a cache flush instruction issued by the normal core, the trusted core initiates and executes a second cache write-back instruction that is different from the first cache write-back instruction. According to the second cache write-back instruction, isolated data associated with the isolated storage space and cached in the shared cache is written back to the isolated storage space before being flushed.

Abstract: A processor for building a homogeneous dual computing system is shown. The processor provides two homogeneous cores. One is used as a trusted core and the other is used as a master core. The trusted core has an access right to an isolated storage space of a system memory. The master core is a normal core that is prohibited from accessing the isolated storage space. The trusted core has a first cryptographic module. In response to a reset of the trusted core, the first cryptographic module operates for firmware verification. This is how the trusted core turns on the processor using trusted firmware.