Patents by Inventor Yinghao HO

Yinghao HO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10707219
    Abstract: A semiconductor integrated circuit of an embodiment includes: first to fifth wiring lines; a first OTP memory element including a first and second terminals connected to the first and second wiring lines; a first p-channel transistor including a source and drain terminals connected to the first and third wiring line, and a gate terminal receiving a first control signal; a first n-channel transistor including a source and drain terminals connected to the first and fourth wiring lines, and a gate terminal receiving a second control signal; a second p-channel transistor including a source and drain terminals connected to the second and third wiring lines, and a gate terminal receiving a third control signal; and a second n-channel transistor including a source and drain terminals connected to the second and fifth wiring lines, and a gate terminal receiving a fourth control signal.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: July 7, 2020
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yinghao Ho, Masato Oda, Shinichi Yasuda
  • Publication number: 20200083235
    Abstract: A semiconductor integrated circuit of an embodiment includes: first to fifth wiring lines; a first OTP memory element including a first and second terminals connected to the first and second wiring lines; a first p-channel transistor including a source and drain terminals connected to the first and third wiring line, and a gate terminal receiving a first control signal; a first n-channel transistor including a source and drain terminals connected to the first and fourth wiring lines, and a gate terminal receiving a second control signal; a second p-channel transistor including a source and drain terminals connected to the second and third wiring lines, and a gate terminal receiving a third control signal; and a second n-channel transistor including a source and drain terminals connected to the second and fifth wiring lines, and a gate terminal receiving a fourth control signal.
    Type: Application
    Filed: March 8, 2019
    Publication date: March 12, 2020
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yinghao HO, Masato Oda, Shinichi Yasuda
  • Patent number: 10424377
    Abstract: A semiconductor integrated circuit according to an embodiment includes: first to third wirings; first current limiters corresponding to the first wirings; second current limiters corresponding to the second wirings; third current limiters corresponding to the third wirings; first drivers corresponding to the first current limiters; second drivers corresponding to the second current limiters; third drivers corresponding to the third current limiters; and a first array and a second array, wherein the first array comprising: fourth wirings corresponding to the first wirings; fifth wirings corresponding to the second wirings; first transistors corresponding to the first wirings; second transistors corresponding to the second wirings; and first resistive change elements arranged in intersecting areas of the fourth wirings and the fifth wirings, respectively, the first resistive change elements including a first terminal connected to corresponding one of the fourth wirings and a second terminal connected to corresp
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: September 24, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yinghao Ho, Masato Oda, Kosuke Tatsumura, Shinichi Yasuda
  • Publication number: 20190080758
    Abstract: A semiconductor integrated circuit according to an embodiment includes: first to third wirings; first current limiters corresponding to the first wirings; second current limiters corresponding to the second wirings; third current limiters corresponding to the third wirings; first drivers corresponding to the first current limiters; second drivers corresponding to the second current limiters; third drivers corresponding to the third current limiters; and a first array and a second array, wherein the first array comprising: fourth wirings corresponding to the first wirings; fifth wirings corresponding to the second wirings; first transistors corresponding to the first wirings; second transistors corresponding to the second wirings; and first resistive change elements arranged in intersecting areas of the fourth wirings and the fifth wirings, respectively, the first resistive change elements including a first terminal connected to corresponding one of the fourth wirings and a second terminal connected to corresp
    Type: Application
    Filed: February 28, 2018
    Publication date: March 14, 2019
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yinghao HO, Masato ODA, Kosuke TATSUMURA, Shinichi YASUDA
  • Patent number: 10090049
    Abstract: An integrated circuit according to an embodiment includes: resistive change elements disposed in intersection regions between first and second wiring lines; a first driver driving the first wiring lines; a second driver driving the second wiring lines; a control circuit controlling the first and second drivers; first current limiter circuits corresponding to the first wiring lines, each of the first current circuits each limiting a maximum current flowing in corresponding one of the first wiring lines to a value not greater than one of a first to third current values; and second current limiter circuits corresponding to the second wiring lines, the second current limiter circuits each limiting a maximum current flowing in corresponding one of the second wiring lines to a value not greater than one of the first to third current value, the limiting current of the selected element being higher than that of the unselected element.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: October 2, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yinghao Ho, Shinichi Yasuda
  • Publication number: 20180151225
    Abstract: An integrated circuit according to an embodiment includes: resistive change elements disposed in intersection regions between first and second wiring lines; a first driver driving the first wiring lines; a second driver driving the second wiring lines; a control circuit controlling the first and second drivers; first current limiter circuits corresponding to the first wiring lines, each of the first current circuits each limiting a maximum current flowing in corresponding one of the first wiring lines to a value not greater than one of a first to third current values; and second current limiter circuits corresponding to the second wiring lines, the second current limiter circuits each limiting a maximum current flowing in corresponding one of the second wiring lines to a value not greater than one of the first to third current value, the limiting current of the selected element being higher than that of the unselected element.
    Type: Application
    Filed: September 11, 2017
    Publication date: May 31, 2018
    Inventors: Yinghao HO, Shinichi YASUDA
  • Publication number: 20170271404
    Abstract: A programmable logic device according to an embodiment includes: a plurality of first and second wiring lines; a plurality of resistive change elements each including a first electrode containing Ni and connected to corresponding one of the first wiring lines, a second electrode containing TiN and connected to corresponding one of the second wiring lines, a resistive change layer containing a hafnium oxide and arranged between the first electrode and the second electrode, and an insulation layer arranged between the resistive change layer and the second electrode, the insulation layer including at least one of an aluminum oxide, an iron oxide, a titanium oxide, a copper oxide, a nickel oxide, a tantalum oxide, a tungsten oxide, a chromium oxide, a rhenium oxide, and a hafnium oxynitride.
    Type: Application
    Filed: September 15, 2016
    Publication date: September 21, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yinghao HO, Koichiro Zaitsu, Shinichi Yasuda
  • Patent number: 9646665
    Abstract: A look-up table circuit of an embodiment includes: first wiring lines; second wiring lines; resistive change elements disposed to intersection regions of the first and second wiring lines, each resistive change element including a first electrode connected to a corresponding one of the first wiring lines, a second electrode connected to a corresponding one of the second wiring lines; and a resistive change layer disposed between the first electrode and the second electrode; a first controller controlling voltages applied to the first wiring lines; a second controller controlling voltages applied to the second wiring lines; and a multiplexer including input terminals connected to the first wiring lines and an output terminal.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: May 9, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yinghao Ho, Koichiro Zaitsu, Shinichi Yasuda, Kosuke Tatsumura
  • Publication number: 20160203860
    Abstract: A look-up table circuit of an embodiment includes: first wiring lines; second wiring lines; resistive change elements disposed to intersection regions of the first and second wiring lines, each resistive change element including a first electrode connected to a corresponding one of the first wiring lines, a second electrode connected to a corresponding one of the second wiring lines; and a resistive change layer disposed between the first electrode and the second electrode; a first controller controlling voltages applied to the first wiring lines; a second controller controlling voltages applied to the second wiring lines; and a multiplexer including input terminals connected to the first wiring lines and an output terminal.
    Type: Application
    Filed: January 5, 2016
    Publication date: July 14, 2016
    Inventors: Yinghao HO, Koichiro ZAITSU, Shinichi YASUDA, Kosuke TATSUMURA