Abstract: A semiconductor circuit device in which a plurality of target circuits are provided and a control signal for controlling enable and disable is input to each of the plurality of target circuits, the device includes: a gating control circuit provided for each of the plurality of target circuits, in which the control signal to the corresponding target circuit is input and an On signal is output in response to the control signal for enabling the target circuit; and a power gate switch for each of the plurality of target circuits, which is provided on each power line for each of the plurality of target circuits for supplying a driving voltage to the target circuit and turned on by the On signal.

Abstract: A semiconductor circuit device includes a first clock gating circuit that outputs a first gated clock signal generated from a clock signal and a first enable signal, a non-volatile first flip-flop that operates in response to a clock pulse of the first gated clock signal, an acquisition circuit that acquires data inputted from the first flip-flop according to a second enable signal that enables or disables the acquisition of the data from the first flip-flop, and a power gating circuit that supplies electric power to the first flip-flop and receives the first and second enable signals as power source control signals. The power gating circuit includes a power switch, and supplies the electric power to the first flip-flop by turning ON the power switch when the power source control signals have logical values that enable the clock signal or the acquisition of the data in the acquisition circuit.

Abstract: A computation processing device includes: a convolutional computation unit that sequentially outputs convolutional computation result data; a pooling processing unit including a pooling computation circuit and a non-volatile storage circuit for pooling, in which the non-volatile storage circuit for pooling retains the convolutional computation result data or a computation result of the pooling computation circuit, as retained data, and the pooling computation circuit calculates and outputs pooling data subjected to pooling processing to a pooling region by using the retained data each time when the convolutional computation result data is input from the convolutional computation unit; and a power gating unit that blocks power supply to the non-volatile storage circuit for pooling while waiting for the input of the convolutional computation result data from the convolutional computation unit.

Abstract: A clustering device includes: an evaluation score calculation section configured to calculate an evaluation score or evaluation scores for evaluating a classification result; a batch process section configured to classify multiple element data into clusters with an optimum number of clusters, based on the evaluation scores respectively obtained for different number of clusters by assigning each of the multiple element data to one of the clusters; an update process section configured to assign newly added element data to a cluster that is closest to the newly added element data among the clusters into which the multiple element data are classified by the batch process section; and a determination section configured to determine validity of a classification result after assigning the newly added element data to the cluster, based on the evaluation score obtained by assigning the newly added element data to the cluster by the update process section.

Abstract: There is provided a neural network circuit device including a plurality of synapse circuits storing a synaptic coupling weight and a neuron circuit connected to the plurality of synapse circuits. The plurality of synapse circuits store the synaptic coupling weight in a non-volatile manner and output a voltage signal having a magnitude based on the stored synaptic coupling weight in response to an input signal. The neuron circuit includes a neuron MOS transistor having a floating gate and a plurality of control gates which are capacitively coupled to the floating gate and to which the voltage signals from the plurality of synapse circuits are input respectively, and a pulse generator outputting a pulse signal by turning on or off the neuron MOS transistor.

Abstract: A semiconductor circuit device includes a first clock gating circuit that outputs a first gated clock signal generated from a clock signal and a first enable signal, a non-volatile first flip-flop that operates in response to a clock pulse of the first gated clock signal, an acquisition circuit that acquires data inputted from the first flip-flop according to a second enable signal that enables or disables the acquisition of the data from the first flip-flop, and a power gating circuit that supplies electric power to the first flip-flop and receives the first and second enable signals as power source control signals. The power gating circuit includes a power switch, and supplies the electric power to the first flip-flop by turning ON the power switch when the power source control signals have logical values that enable the clock signal or the acquisition of the data in the acquisition circuit.

Abstract: Provided is a simplified driving method of a synapse circuit. In a case where a first pre-spike pulse precedes a first post-spike pulse, a second pre-spike pulse from an input circuit 20a is used as a time window that allows writing of a coupling weight, and the first post-spike pulse from a neuron circuit 17 is used as a write pulse for controlling a write timing of the coupling weight. In a case where the first post-spike pulse precedes the first pre-spike pulse, a second post-spike pulse from the neuron circuit 17 is used as the time window, and the first pre-spike pulse from the input circuit 20a is used as the write pulse. The second pre-spike pulse and the second post-spike pulse are output in synchronization with the first pre-spike pulse and the first post-spike pulse, respectively.

Abstract: There is provided a neural network circuit device including a plurality of synapse circuits storing a synaptic coupling weight and a neuron circuit connected to the plurality of synapse circuits. The plurality of synapse circuits store the synaptic coupling weight in a non-volatile manner and output a voltage signal having a magnitude based on the stored synaptic coupling weight in response to an input signal. The neuron circuit includes a neuron MOS transistor having a floating gate and a plurality of control gates which are capacitively coupled to the floating gate and to which the voltage signals from the plurality of synapse circuits are input respectively, and a pulse generator outputting a pulse signal by turning on or off the neuron MOS transistor.

Abstract: A clustering device includes: an evaluation score calculation section configured to calculate an evaluation score or evaluation scores for evaluating a classification result; a batch process section configured to classify multiple element data into clusters with an optimum number of clusters, based on the evaluation scores respectively obtained for different number of clusters by assigning each of the multiple element data to one of the clusters; an update process section configured to assign newly added element data to a cluster that is closest to the newly added element data among the clusters into which the multiple element data are classified by the batch process section; and a determination section configured to determine validity of a classification result after assigning the newly added element data to the cluster, based on the evaluation score obtained by assigning the newly added element data to the cluster by the update process section.

Abstract: A memory device capable of reading reference data while achieving optimization of electric power consumption is provided. A memory device includes a memory area storing reference data of N (?1) dimensions each composed of M (?1) bits. A number of memory grains each composed of nonvolatile memory and power drivers paired with the memory grains to supply electrical power to the memory grains are provided in each region specified by column lines in the number and M row lines, the number being one to N inclusive. When the power driver receives a control signal from the corresponding one of the column lines, a control signal from the corresponding one of the M row lines, and a clock signal, the power driver supplies electrical power to the memory grain in synchronization with the clock signal.

Abstract: A memory device capable of reading reference data while achieving optimization of electric power consumption is provided. A memory device includes a memory area storing reference data of N (?1) dimensions each composed of M (?1) bits. A number of memory grains each composed of nonvolatile memory and power drivers paired with the memory grains to supply electrical power to the memory grains are provided in each region specified by column lines in the number and M row lines, the number being one to N inclusive. When the power driver receives a control signal from the corresponding one of the column lines, a control signal from the corresponding one of the M row lines, and a clock signal, the power driver supplies electrical power to the memory grain in synchronization with the clock signal.

Abstract: A memory device and a memory system capable of flexibly corresponding to the number of dimensions of reference data and having a compact circuit configuration at searching for data similar to search data are provided. A memory system capable of reducing processing time to search for data similar to search data and reducing a circuit area is provided. A memory device includes a plurality of read circuits, an input search data storing circuit configured to divide search data to output, a plurality of similarity evaluation cells and a plurality of current accumulators. The memory system is configured by including a main core and a branch core thus configured.

Abstract: A memory device and a memory system capable of flexibly corresponding to the number of dimensions of reference data and having a compact circuit configuration at searching for data similar to search data are provided. A memory system capable of reducing processing time to search for data similar to search data and reducing a circuit area is provided. A memory device includes a plurality of read circuits, an input search data storing circuit configured to divide search data to output, a plurality of similarity evaluation cells and a plurality of current accumulators. The memory system is configured by including a main core and a branch core thus configured.