Patents by Inventor Yo-Sep LEE

Yo-Sep LEE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220375900
    Abstract: A stacked semiconductor device includes a plurality of stacked semiconductor dies electrically connected with each other, a first power line electrically connected to a lowermost semiconductor die among the stacked semiconductor dies, a second power line formed over an uppermost semiconductor die among the stacked semiconductor dies, and an external connection line electrically connecting the first power line and the second power line.
    Type: Application
    Filed: December 10, 2021
    Publication date: November 24, 2022
    Applicant: SK hynix Inc.
    Inventor: Yo Sep LEE
  • Publication number: 20220244889
    Abstract: A memory device includes a data storage circuit configured to access a cell array having first data stored therein when an arithmetic active operation is performed, output the first data when a first read operation is performed, access a cell array having second data stored therein when an active operation is performed, and output the second data when a second read operation is performed. The memory device also includes an arithmetic circuit configured to receive latch data generated through the first read operation and read data generated through the second read operation, and perform an arithmetic operation on the latch data and the read data.
    Type: Application
    Filed: May 24, 2021
    Publication date: August 4, 2022
    Applicant: SK hynix Inc.
    Inventor: Yo Sep LEE
  • Patent number: 11289174
    Abstract: A stacked semiconductor device including a plurality of semiconductor chips that are stacked and transfer signals through a plurality of through-electrodes, wherein at least one of the semiconductor chips comprises a first clock generation circuit suitable for generating first and second test clocks by dividing or buffering an external clock according to an operating information signal for indicating a high-speed test operation and a low-speed test operation; a first latch circuit suitable for latching a test control signal according to the first and second test clocks to generate first and second latched signals; and an input signal control circuit suitable for generating first and second internal control signals by re-latching the second latched signal according to the first test clock, and re-latching the first latched signal according to the second test clock.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: March 29, 2022
    Assignee: SK hynix Inc.
    Inventors: Yo-Sep Lee, Dong-Ha Lee, Seon-Woo Hwang
  • Patent number: 11222684
    Abstract: A refresh control device, and a memory device may be provided. The latch controller may include a first oscillator configured to generate a first oscillation signal, and a second oscillator configured to generate a second oscillation signal. The latch controller may be configured to receive a precharge signal and prevent the second oscillation signal from being synchronized with the precharge signal.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: January 11, 2022
    Assignee: SK hynix Inc.
    Inventors: Jae Seung Lee, Chang Hyun Kim, Yo Sep Lee
  • Patent number: 11139041
    Abstract: A stacked semiconductor device includes semiconductor chips, each including a signal transfer circuit respectively transferring a command, an address, and a chip select signal to first to third through electrodes, and respectively transferring a test address and a chip ID to the second and third through electrodes according to a test control signal; a command reception circuit transferring a test command or a signal transferred from the first through electrode to an internal circuit when a signal transferred from the third through electrode is identical to the chip ID coincide with each other; and a test control circuit activating the test control signal according to deactivation of a test control signal of an upper chip, and generating the test command and the test address according to the test control signal.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: October 5, 2021
    Assignee: SK hynix Inc.
    Inventor: Yo-Sep Lee
  • Publication number: 20210193253
    Abstract: A stacked semiconductor device including a plurality of semiconductor chips that are stacked and transfer signals through a plurality of through-electrodes, wherein at least one of the semiconductor chips comprises a first clock generation circuit suitable for generating first and second test clocks by dividing or buffering an external clock according to an operating information signal for indicating a high-speed test operation and a low-speed test operation; a first latch circuit suitable for latching a test control signal according to the first and second test clocks to generate first and second latched signals; and an input signal control circuit suitable for generating first and second internal control signals by re-latching the second latched signal according to the first test clock, and re-latching the first latched signal according to the second test clock.
    Type: Application
    Filed: April 15, 2020
    Publication date: June 24, 2021
    Inventors: Yo-Sep LEE, Dong-Ha LEE, Seon-Woo HWANG
  • Patent number: 10867656
    Abstract: A memory includes: first to Nth areas refreshed based on first to Nth refresh control signals, respectively; a control signal generation circuit suitable for generating the second to Nth refresh control signals by sequentially delaying the first refresh control signal, and generating the first refresh control signal by delaying the Nth refresh control signal; an address counter suitable for changing a refresh address, corresponding to each round for activations of the first to Nth refresh control signals, based on the Nth refresh control signal; and a refresh stop circuit suitable for stopping a refresh operation when the round is repeated by a predetermined number.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: December 15, 2020
    Assignee: SK hynix Inc.
    Inventor: Yo-Sep Lee
  • Publication number: 20200303030
    Abstract: A stacked semiconductor device includes semiconductor chips, each including a signal transfer circuit respectively transferring a command, an address, and a chip select signal to first to third through electrodes, and respectively transferring a test address and a chip ID to the second and third through electrodes according to a test control signal; a command reception circuit transferring a test command or a signal transferred from the first through electrode to an internal circuit when a signal transferred from the third through electrode is identical to the chip ID coincide with each other; and a test control circuit activating the test control signal according to deactivation of a test control signal of an upper chip, and generating the test command and the test address according to the test control signal.
    Type: Application
    Filed: October 30, 2019
    Publication date: September 24, 2020
    Inventor: Yo-Sep LEE
  • Publication number: 20200098418
    Abstract: A refresh control device, and a memory device may be provided. The latch controller may include a first oscillator configured to generate a first oscillation signal, and a second oscillator configured to generate a second oscillation signal. The latch controller may be configured to receive a precharge signal and prevent the second oscillation signal from being synchronized with the precharge signal.
    Type: Application
    Filed: November 26, 2019
    Publication date: March 26, 2020
    Applicant: SK hynix Inc.
    Inventors: Jae Seung LEE, Chang Hyun KIM, Yo Sep LEE
  • Publication number: 20200090733
    Abstract: A memory includes: first to Nth areas refreshed based on first to Nth refresh control signals, respectively; a control signal generation circuit suitable for generating the second to Nth refresh control signals by sequentially delaying the first refresh control signal, and generating the first refresh control signal by delaying the Nth refresh control signal; an address counter suitable for changing a refresh address, corresponding to each round for activations of the first to Nth refresh control signals, based on the Nth refresh control signal; and a refresh stop circuit suitable for stopping a refresh operation when the round is repeated by a predetermined number.
    Type: Application
    Filed: May 31, 2019
    Publication date: March 19, 2020
    Inventor: Yo-Sep LEE
  • Patent number: 10529405
    Abstract: A refresh control device, and a memory device may be provided. The latch controller may include a first oscillator configured to generate a first oscillation signal, and a second oscillator configured to generate a second oscillation signal. The latch controller may be configured to receive a precharge signal and prevent the second oscillation signal from being synchronized with the precharge signal.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: January 7, 2020
    Assignee: SK hynix Inc.
    Inventors: Jae Seung Lee, Chang Hyun Kim, Yo Sep Lee
  • Patent number: 10475486
    Abstract: An electronic device includes a pulse generator, a signal synthesizer, and a first storage circuit. The pulse generator generates a mode active pulse and a mode pre-charge pulse in response to an operation mode signal. The signal synthesizer synthesizes an active signal and the mode active pulse to generate a synthesized active signal. The signal synthesizer synthesizes a pre-charge signal and the mode pre-charge pulse to generate a synthesized pre-charge signal. The first storage circuit performs an active operation, a read operation, or a pre-charge operation in response to the synthesized active signal, a read signal, and the synthesized pre-charge signal in each of a first read mode and a second read mode.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: November 12, 2019
    Assignee: SK hynix Inc.
    Inventor: Yo Sep Lee
  • Patent number: 10388336
    Abstract: A semiconductor apparatus includes a decoder configured to decode an internal command, and generate a first decoding command and a second decoding command. The semiconductor apparatus may include an output timing control circuit configured to delay the second decoding command by a predetermined cycle of the internal clock, and output a delayed decoding command. The semiconductor apparatus may include an input/output control latch circuit configured to output the internal address as a first latch address based on the second decoding command and the delayed decoding command. The semiconductor apparatus may include an input control latch circuit configured to output the internal address as a second latch address based on the first decoding command.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: August 20, 2019
    Assignee: SK hynix Inc.
    Inventor: Yo Sep Lee
  • Publication number: 20190237115
    Abstract: A semiconductor apparatus includes a decoder configured to decode an internal command, and generate a first decoding command and a second decoding command. The semiconductor apparatus may include an output timing control circuit configured to delay the second decoding command by a predetermined cycle of the internal clock, and output a delayed decoding command. The semiconductor apparatus may include an input/output control latch circuit configured to output the internal address as a first latch address based on the to second decoding command and the delayed decoding command. The semiconductor apparatus may include an input control latch circuit configured to output the internal address as a second latch address based on the first decoding command.
    Type: Application
    Filed: April 5, 2019
    Publication date: August 1, 2019
    Applicant: SK hynix Inc.
    Inventor: Yo Sep LEE
  • Patent number: 10297293
    Abstract: A semiconductor apparatus includes a decoder configured to decode an internal command, and generate a first decoding command and a second decoding command. The semiconductor apparatus may include an output timing control circuit configured to delay the second decoding command by a predetermined cycle of the internal clock, and output a delayed decoding command. The semiconductor apparatus may include an input/output control latch circuit configured to output the internal address as a first latch address based on the second decoding command and the delayed decoding command. The semiconductor apparatus may include an input control latch circuit configured to output the internal address as a second latch address based on the first decoding command.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: May 21, 2019
    Assignee: SK hynix Inc.
    Inventor: Yo Sep Lee
  • Publication number: 20190027198
    Abstract: An electronic device includes a pulse generator, a signal synthesizer, and a first storage circuit. The pulse generator generates a mode active pulse and a mode pre-charge pulse in response to an operation mode signal. The signal synthesizer synthesizes an active signal and the mode active pulse to generate a synthesized active signal. The signal synthesizer synthesizes a pre-charge signal and the mode pre-charge pulse to generate a synthesized pre-charge signal. The first storage circuit performs an active operation, a read operation, or a pre-charge operation in response to the synthesized active signal, a read signal, and the synthesized pre-charge signal in each of a first read mode and a second read mode.
    Type: Application
    Filed: January 12, 2018
    Publication date: January 24, 2019
    Applicant: SK hynix Inc.
    Inventor: Yo Sep LEE
  • Publication number: 20180261276
    Abstract: A refresh control device, and a memory device may be provided. The latch controller may include a first oscillator configured to generate a first oscillation signal, and a second oscillator configured to generate a second oscillation signal. The latch controller may be configured to receive a precharge signal and prevent the second oscillation signal from being synchronized with the precharge signal.
    Type: Application
    Filed: May 10, 2018
    Publication date: September 13, 2018
    Applicant: SK hynix Inc.
    Inventors: Jae Seung LEE, Chang Hyun KIM, Yo Sep LEE
  • Publication number: 20180218776
    Abstract: An integrated circuit including semiconductor devices may be provided. The semiconductor device may be configured to compare phases of strobe signals which are generated according to internal delay times of the semiconductor devices and configured to control points of time that an internal command is inputted to the internal circuits of the semiconductor devices according to a comparison result of the phases of the strobe signals.
    Type: Application
    Filed: July 18, 2017
    Publication date: August 2, 2018
    Applicant: SK hynix Inc.
    Inventors: Chang Hyun KIM, Kibong KOO, Choung Ki SONG, Byung Kuk YOON, Yo Sep LEE, Jae Seung LEE
  • Patent number: 10037811
    Abstract: An integrated circuit including semiconductor devices may be provided. The semiconductor device may be configured to compare phases of strobe signals which are generated according to internal delay times of the semiconductor devices and configured to control points of time that an internal command is inputted to the internal circuits of the semiconductor devices according to a comparison result of the phases of the strobe signals.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: July 31, 2018
    Assignee: SK hynix Inc.
    Inventors: Chang Hyun Kim, Kibong Koo, Choung Ki Song, Byung Kuk Yoon, Yo Sep Lee, Jae Seung Lee
  • Publication number: 20180166117
    Abstract: An operating method of a memory device including a plurality of memory cells may include: measuring data retention times of at least a portion of the plurality of memory cells; and optimizing a refresh operation on the plurality of memory cells using the measurement result.
    Type: Application
    Filed: August 21, 2017
    Publication date: June 14, 2018
    Inventors: Hae-Rang CHOI, Youk-Hee KIM, Jae-Seung LEE, Mi-Hyeon JO, Dong-Jae LEE, Kyeong-Pil KANG, Sung-Soo CHI, Hyung-Sik WON, Hun-Sam JUNG, Yo-Sep LEE