Patents by Inventor Yogendra Ranade

Yogendra Ranade has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130203483
    Abstract: A virtual currency based online social wagering system and method, based on at least one wagering networks server. The system can handle wagers initiated by multiple users using commonly available computerized devices such as Smartphones. The system avoids legal problems through the use of virtual currency rather than money (which makes the interactions wager-like events, rather than actual wagers), and facilitates interactions between friends by drawing upon social networks for much of the interactions. The system is also designed to make friendly social interactions such as banter, “trash talk”, or “swagger” a key part of the wagering experience. Various internal controls insure that the virtual funds are managed correctly.
    Type: Application
    Filed: February 2, 2013
    Publication date: August 8, 2013
    Inventors: Ashish Joshi, Yogendra Ranade
  • Patent number: 7354790
    Abstract: A method and apparatus for avoiding dicing chip-outs in integrated circuit die comprises: (a) providing a wafer for forming a plurality of integrated circuit die thereon; (b) forming the plurality of integrated circuit die on the wafer; and (c) forming a saw street between the integrated circuit die on the wafer to relieve cutting stress in the wafer when the integrated circuit die are separated by a dicing saw.
    Type: Grant
    Filed: May 18, 2005
    Date of Patent: April 8, 2008
    Assignee: LSI Logic Corporation
    Inventors: Parthasarathy Rajagopalan, Zafer Kutlu, Emery O. Sugasawara, Charles E. Vonderach, Dilip P. Vijay, Yogendra Ranade, Jeff Hall, Dwight Manning
  • Publication number: 20070013068
    Abstract: An integrated circuit package and method exploit the volume enclosed by the package substrate vias. In one embodiment, an integrated circuit package includes a first substrate having electrically conductive layers formed on substantially parallel surfaces of the first substrate, a second substrate having electrically conductive layers formed on substantially parallel surfaces of the second substrate, a substrate via formed through the first substrate and the second substrate to form an electrical connection between at least two electrically conductive layers of the first substrate and between at least two electrically conductive layers of the second substrate, an electrical component having a first end and a second end inserted into the substrate via so that the first end extends at least partially inside the first substrate and the second end extends at least partially inside the second substrate, and an electrically insulating layer formed between the first substrate and the second substrate.
    Type: Application
    Filed: June 17, 2005
    Publication date: January 18, 2007
    Inventors: Yogendra Ranade, Parthasarathy Rajagopalan, Jeff Hall
  • Patent number: 7145232
    Abstract: A semiconductor package construction aimed at improving thermal performance. A heatspreader is provided having a metal alloy preform attached to it already. Then, a few dots of conductive epoxy are dispensed around the die. The heatspreader with the preformed metal alloy is pressed on the adhesive and then the part is cured. By coupling the die to the heatspreader with conductive epoxy, the die is constrained from warping. By removing the necessity of coating the die, the cost of fabrication is reduced. There is only a very marginal cost increase in the back end for dispensing the dots. For this, the process and equipment already exists in the backend. By reducing die backside warpage due, the die remains in good contact with the heatspreader, thus improving thermal performance.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: December 5, 2006
    Assignee: LSI Logic Corporation
    Inventors: Rajagopalan Parthasarathy, Kishore Desai, Yogendra Ranade
  • Publication number: 20060160269
    Abstract: A method and apparatus for avoiding dicing chip-outs in integrated circuit die comprises: (a) providing a wafer for forming a plurality of integrated circuit die thereon; (b) forming the plurality of integrated circuit die on the wafer; and (c) forming a saw street between the integrated circuit die on the wafer to relieve cutting stress in the wafer when the integrated circuit die are separated by a dicing saw.
    Type: Application
    Filed: May 18, 2005
    Publication date: July 20, 2006
    Inventors: Parthasarathy Rajagopalan, Zafer Kutlu, Emery Sugasawara, Charles Vonderach, Dilip Vijay, Yogendra Ranade, Jeff Hall, Dwight Manning
  • Publication number: 20060131283
    Abstract: A method and apparatus for making angled vias in an integrated circuit package substrate includes providing an integrated circuit package substrate having an upper surface and a lower surface. A first position is selected for a first via opening on the upper surface of the package substrate, and a second position is selected for a second via opening on the lower surface of the package substrate. A selected non-vertical angle is determined for forming an angled via through the first position and the second position. The angled via is formed through the first position and the second position at the selected non-vertical angle.
    Type: Application
    Filed: December 17, 2004
    Publication date: June 22, 2006
    Inventors: Jeffrey Hall, Yogendra Ranade, Sarathy Rajagopalan
  • Publication number: 20060071327
    Abstract: A semiconductor package construction aimed at improving thermal performance. A heatspreader is provided having a metal alloy preform attached to it already. Then, a few dots of conductive epoxy are dispensed around the die. The heatspreader with the preformed metal alloy is pressed on the adhesive and then the part is cured. By coupling the die to the heatspreader with conductive epoxy, the die is constrained from warping. By removing the necessity of coating the die, the cost of fabrication is reduced. There is only a very marginal cost increase in the back end for dispensing the dots. For this, the process and equipment already exists in the backend. By reducing die backside warpage due, the die remains in good contact with the heatspreader, thus improving thermal performance.
    Type: Application
    Filed: September 30, 2004
    Publication date: April 6, 2006
    Inventors: Rajagopalan Parthasarathy, Kishore Desai, Yogendra Ranade
  • Publication number: 20060043603
    Abstract: Techniques for utilizing a bonding agent that allows a solder reflow process to occur at a lower reflow temperature. One area of use includes semiconductor device manufacturing processes. The bonding agent is placed between a solder ball and a contact surface. The bonding agent has a melting temperature that is lower than that of the solder ball. Reflow is then performed at a relative low temperature that is high enough for reflowing the bonding agent, yet at the same time, lower than what would be necessary to reflow the solder material. Since, the electrical system is not subjected to the high temperatures necessary for reflowing the solder material, the electronic system experiences less high-temperature related damage.
    Type: Application
    Filed: August 31, 2004
    Publication date: March 2, 2006
    Applicant: LSI Logic Corporation
    Inventors: Yogendra Ranade, Rajagopalan Parthasarathy, Jeffrey Hall
  • Patent number: 6825066
    Abstract: A stiffener for reinforcing a package integrated circuit. The stiffener includes a rigid planar element having a first surface for bonding to a package substrate. The rigid planar element forms a major interior aperture for receiving and surrounding an integrated circuit on all sides of the integrated circuit. The rigid planar element also forms a minor interior aperture for receiving and surrounding a secondary circuit structure on at least three sides of the secondary circuit structure. In this manner, the stiffener provides structural support to the integrated circuit package, which reduces and preferably eliminates twisting and warping of the substrate package as it heats and is subjected to other stresses.
    Type: Grant
    Filed: December 3, 2002
    Date of Patent: November 30, 2004
    Assignee: LSI Logic Corporation
    Inventors: Yogendra Ranade, Anand Govind, Kumar Nagarajan, Farshad Ghahghahi, Aritharan Thurairajaratnam
  • Patent number: 6759921
    Abstract: The present invention provides a characteristic impedance equalizer and method of manufacture thereof for use with an integrated circuit package having first and second signal transmission zones. In one embodiment, the characteristic impedancs equalizer includes a first conductor having a first width and providing a characteristic impedance within the first signal transmission zone. The characteristic impedance equalizer also includes a second conductor, coupled to the first conductor, having a second width and providing substantially the same characteristic impedance within the second signal transmission zone.
    Type: Grant
    Filed: August 17, 2001
    Date of Patent: July 6, 2004
    Assignee: LSI Logic Corporation
    Inventors: Anand Govind, Yogendra Ranade
  • Publication number: 20040105241
    Abstract: A stiffener for reinforcing a package integrated circuit. The stiffener includes a rigid planar element having a first surface for bonding to a package substrate. The rigid planar element forms a major interior aperture for receiving and surrounding an integrated circuit on all sides of the integrated circuit. The rigid planar element also forms a minor interior aperture for receiving and surrounding a secondary circuit structure on at least three sides of the secondary circuit structure. In this manner, the stiffener provides structural support to the integrated circuit package, which reduces and preferably eliminates twisting and warping of the substrate package as it heats and is subjected to other stresses.
    Type: Application
    Filed: December 3, 2002
    Publication date: June 3, 2004
    Inventors: Yogendra Ranade, Anand Govind, Kumar Nagarajan, Farshad Ghahghahi, Aritharan Thurairajaratnam
  • Publication number: 20040099962
    Abstract: A substrate which includes an upper and lower surface. The substrate also includes a center or interior portion and a peripheral portion. The upper surface is contoured at the center portion. Solder bumps extend from the upper surface and are positioned in the center portion, and solder bumps extend from the upper surface and are positioned in the peripheral portion. Additional solder material is added to the solder bumps. By adding the additional solder material to the solder bumps, a planar surface is provided by the upper surfaces of the center solder bumps and the peripheral solder bumps. Adding solder to the solder bumps in the periphery portion compensates for the die area planarity differences between the center portion and the periphery portion. As a result of adding solder, planarity issues between the die and the substrate are reduced. Thus, yield losses due to opens in the flipchip joints are also decreased.
    Type: Application
    Filed: November 22, 2002
    Publication date: May 27, 2004
    Inventors: Sarathy Rajagopalan, Yogendra Ranade