Abstract: According to an aspect of an embodiment, operations may include displaying a electronic user interface that includes a plurality of user-selectable options corresponding to taxonomy information for a plurality of optimization problems. The operations may further include receiving a first user input selecting a first template for a specific optimization problem of the plurality of optimization problems. The first user input may include a selection of at least one user-selectable option of the plurality of user-selectable options. The operations may further include receiving a second user input via the selected first template for the specific optimization problem and providing a call to the optimization solver machine to generate a solution for the specific optimization problem based on the received second user input. The second user input may include input data for a plurality of parameters of the specific optimization problem, specified in the selected first template.

Abstract: According to an aspect of an embodiment, operations may include displaying a electronic user interface that includes a plurality of user-selectable options corresponding to taxonomy information for a plurality of optimization problems. The operations may further include receiving a first user input selecting a first template for a specific optimization problem of the plurality of optimization problems. The first user input may include a selection of at least one user-selectable option of the plurality of user-selectable options. The operations may further include receiving a second user input via the selected first template for the specific optimization problem and providing a call to the optimization solver machine to generate a solution for the specific optimization problem based on the received second user input. The second user input may include input data for a plurality of parameters of the specific optimization problem, specified in the selected first template.

Abstract: A transmitting circuit includes: a multiplexer configured to output a third digital signal obtained by alternately synthesizing a first digital signal of a predetermined cycle length and a predetermined data rate with a second digital signal of the predetermined cycle length and the predetermined data rate; a first selector configured to output the first digital signal in a first state and output the third digital signal in a second state that is different from the first state; a second selector configured to output the second digital signal in the first state and output the third digital signal in the second state; a first driver circuit configured to output a signal corresponding to a signal output from the first selector; and a second driver circuit configured to output a signal corresponding to a signal output from the second selector.

Abstract: A timing control circuit includes a first variable-delay circuit, a multiplexer, a second variable-delay circuit, a decision circuit, and a control circuit. The first variable-delay circuit receives first data having a first communication speed and delays the first data by a variable delay. The multiplexer receives a first variable-delay circuit output and converts, based on a first control signal, the first data into second data having a second communication speed different from the first communication speed. The second variable-delay circuit receives third data having the first communication speed, and delays the third data by another variable-delay corresponding to the variable-delay of the first variable-delay circuit. The decision circuit compares a second variable-delay circuit output phase and a first control signal phase.

Abstract: Provided is a transmission circuit that includes first and second drive circuits. A first digital signal at a data rate of a predetermined period length is input to the first drive circuit. A second digital signal at the data rate of the predetermined period length shifted by ½ of the predetermined period length relative to the first digital signal is input to second drive circuit. The outputs of the first drive circuit and the second drive circuit are connected. The connected output indicates the maximum level or the minimum level when the value of the first digital signal and the value of the second digital signal are the same. The connected output indicates a level between the maximum level and the minimum level when the value of the first digital signal and the value of the second digital signal are different.

Abstract: A circuit includes: a first adder configured to add a first offset cancellation value to an input signal value; a second adder configured to add a first equalization value to an output signal value from the first adder; a first comparator configured to make a binary decision on an output signal value from the second adder; a third adder configured to add a second offset cancellation value to the input signal value; a fourth adder configured to add a second equalization value to an output signal value from the third adder; a second comparator configured to make a binary decision on an output signal value from the fourth adder; a selector configured to output a determination result of the first comparator or a determination result of the second comparator in accordance with a determination result of preceding one bit of the input signal value.

Abstract: A transmitting circuit includes: a multiplexer configured to output a third digital signal obtained by alternately synthesizing a first digital signal of a predetermined cycle length and a predetermined data rate with a second digital signal of the predetermined cycle length and the predetermined data rate; a first selector configured to output the first digital signal in a first state and output the third digital signal in a second state that is different from the first state; a second selector configured to output the second digital signal in the first state and output the third digital signal in the second state; a first driver circuit configured to output a signal corresponding to a signal output from the first selector; and a second driver circuit configured to output a signal corresponding to a signal output from the second selector.

Abstract: A circuit includes: a first adder configured to add a first offset cancellation value to an input signal value; a second adder configured to add a first equalization value to an output signal value from the first adder; a first comparator configured to make a binary decision on an output signal value from the second adder; a third adder configured to add a second offset cancellation value to the input signal value; a fourth adder configured to add a second equalization value to an output signal value from the third adder; a second comparator configured to make a binary decision on an output signal value from the fourth adder; a selector configured to output a determination result of the first comparator or a determination result of the second comparator in accordance with a determination result of preceding one bit of the input signal value.

Abstract: A timing control circuit includes: a first variable delay circuit configured to receive first data having a first communication speed, and to give a variable delay to the first data; a first multiplexer configured to receive output of the first variable delay circuit, and to convert into second data having a second communication speed different from the first communication speed in accordance with first control signal; a second variable delay circuit configured to receive third data having the first communication speed, and to give a delay corresponding to the delay of the first variable delay circuit to the third data; a decision circuit configured to compare timings of output of the second variable delay circuit and the first control signal; and a control circuit configured to control the delays of the first variable delay circuit and the second variable delay circuit in accordance with output of the decision circuit.

Abstract: A latch circuit switches a differential operation performed by a differential operation circuit including a first logic circuit, a second logic circuit, a third logic circuit, and a fourth logic circuit and a single end operation performed by a single end operation circuit according to a logic level of an inputted selection signal. The latch circuit performs an operation to output an input signal and an inverted input signal without change from a first output terminal and a second output terminal of the latch circuit, respectively, and an operation to set the input signal and the inverted input signal in a hold state in the differential operation and performs an operation to output the input signal from the first output terminal without change and an operation to set the input signal in a hold state in the single end operation, according to a clock signal and an inverted clock signal.

Abstract: A data receiver circuit for converting received serial data into parallel data in accordance with a data rate signal and for outputting the converted parallel data, the data receiver circuit includes a clock generator for generating a reference clock based on an input clock, a data latch for latching the received serial data and outputting first latched serial data in accordance with the reference clock, a first data output section for converting the first latched serial data into first parallel data with a first reference clock, in case that the data rate signal indicates a first data rate same as a data rate of the reference clock, and a second data output section for converting the first latched serial data into second parallel data with a second reference clock, in case that the data rate signal indicates a second data rate slower than the data rate of the reference clock.

Abstract: A parallel-to-serial conversion circuit includes a plurality of parallel-to-serial conversion units, each being configured to include a dividing circuit configured to divide a clock signal having a second clock cycle to generate a clock signal having a first clock cycle, a parallel input circuit configured to input a signal having a plurality of bits parallel to one another in the first clock cycle, and a serial output circuit configured to serially output the signal having the plurality of bits input to the parallel input circuit bit-by-bit in the second clock cycle, wherein, among the plurality of parallel-to-serial conversion units, one of the dividing circuits has a synchronization signal interface that causes an output clock signal to synchronize with a clock signal output from the other dividing circuit in another parallel-to-serial conversion unit.

Abstract: A parallel-to-serial conversion circuit includes a plurality of parallel-to-serial conversion units, each being configured to include a dividing circuit configured to divide a clock signal having a second clock cycle to generate a clock signal having a first clock cycle, a parallel input circuit configured to input a signal having a plurality of bits parallel to one another in the first clock cycle, and a serial output circuit configured to serially output the signal having the plurality of bits input to the parallel input circuit bit-by-bit in the second clock cycle, wherein, among the plurality of parallel-to-serial conversion units, one of the dividing circuits has a synchronization signal interface that causes an output clock signal to synchronize with a clock signal output from the other dividing circuit in another parallel-to-serial conversion unit.

Abstract: A data transmitting circuit that converts parallel data into serial data to output the serial data, includes a first data input port that receives first parallel data at a first data rate based on a reference input clock; a second data input port that receives second parallel data at a second data rate lower than the reference input clock, a data expansion unit that generates expanded data by expanding a bit number of the second parallel data to a bit number of the first parallel data, a serial data generation unit that performs a process for generating first serial data by performing a serial conversion on the first parallel data based on the reference input clock and a process for generating second serial data by performing a serial conversion on the expanded data, and a data output port that outputs the first serial data or the second serial data.

Abstract: A data receiver circuit for converting received serial data into parallel data in accordance with a data rate signal and for outputting the converted parallel data, the data receiver circuit includes a clock generator for generating a reference clock based on an input clock, a data latch for latching the received serial data and outputting first latched serial data in accordance with the reference clock, a first data output section for converting the first latched serial data into first parallel data with a first reference clock, in case that the data rate signal indicates a first data rate same as a data rate of the reference clock, and a second data output section for converting the first latched serial data into second parallel data with a second reference clock, in case that the data rate signal indicates a second data rate slower than the data rate of the reference clock.

Abstract: A data transmitting circuit that converts parallel data into serial data to output the serial data, includes a first data input port that receives first parallel data at a first data rate based on a reference input clock; a second data input port that receives second parallel data at a second data rate lower than the reference input clock, a data expansion unit that generates expanded data by expanding a bit number of the second parallel data to a bit number of the first parallel data, a serial data generation unit that performs a process for generating first serial data by performing a serial conversion on the first parallel data based on the reference input clock and a process for generating second serial data by performing a serial conversion on the expanded data, and a data output port that outputs the first serial data or the second serial data.

Abstract: According to one embodiment of the present invention, a method for equalizing a signal includes receiving a plurality of in incoming data signals. Each of the plurality of incoming data signals have an associated sequence of data. A delay is introduced into the plurality of incoming data signals to generate a plurality of delayed data signals.

Abstract: Equalizing a signal includes receiving a data sequence signal having an amplitude. An adjustment of the data sequence signal operable to equalize the data sequence signal is determined. A control signal operable to adjust the amplitude of the data sequence signal in accordance with the adjustment is generated, where the control signal has an analog form. The amplitude of the data sequence signal is adjusted using the control signal in order to equalize the data sequence signal.

Abstract: A low-voltage differential signal (LVDS) driver includes at least two programmable fingers operable to drive a signal and at least two pre-drivers. Each pre-driver is associated with one or more of the programmable fingers and is operable to enable or disable the associated one or more programmable fingers. An enabled programmable finger drives the signal and contributes to the capacitive loading of the driver, and a disabled programmable finger does not drive the signal and does not contribute to the capacitive loading of the driver.

Abstract: A low-voltage differential signal (LVDS) driver includes at least two programmable fingers operable to drive a signal and at least two pre-drivers. Each pre-driver is associated with one or more of the programmable fingers and is operable to enable or disable the associated one or more programmable fingers. An enabled programmable finger drives the signal and contributes to the capacitive loading of the driver, and a disabled programmable finger does not drive the signal and does not contribute to the capacitive loading of the driver.