Patents by Inventor Yoichiro Ishikawa

Yoichiro Ishikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170297761
    Abstract: The present invention provides an improved product holding and dispensing package and an improved method for manufacturing, holding, and storing products, especially comestible products. In an embodiment, a package for comestible products may be provided. The package includes a package blank having walls that define a package interior. The package also includes a sheet disposed inside the package interior. The sheet wraps around a stack of comestible products and maintains the products in a stacked formation. The sheet also retains the comestible products against lateral movement within the sheet. In an embodiment, the plurality of comestible products are releasably attached to the sheet to prevent the comestible products from sliding out of the sheet. In an embodiment, the sheet may be attached to the package interior.
    Type: Application
    Filed: March 14, 2017
    Publication date: October 19, 2017
    Inventors: Yoichiro Ishikawa, James W. Wolff, Heather L. Fluegel
  • Publication number: 20170183136
    Abstract: A reclosable package configured to contain a plurality of consumable products includes a flexible film blank having a flap portion, a back portion, and a front portion, wherein the flap portion, the back portion and the front portion are contiguously formed portions of the flexible film blank. The package further includes a pocket formed by the cooperation of an inner surface of the front portion and an inner surface of the back portion along a first fold line, wherein the pocket has an opening at the top of the pocket and the flap portion is secured to the pocket on the outer surface of the front portion after being folded along a second fold line to cover the opening and the flap portion is reclosable over the opening.
    Type: Application
    Filed: February 12, 2015
    Publication date: June 29, 2017
    Applicant: WM. WRIGLEY JR. COMPANY
    Inventors: Russell L. STACY-RYAN, Yoichiro ISHIKAWA
  • Patent number: 9630740
    Abstract: The present invention provides an improved product holding and dispensing package and an improved method for manufacturing, holding, and storing products, especially comestible products. In an embodiment, a package for comestible products may be provided. The package includes a package blank having walls that define a package interior. The package also includes a sheet disposed inside the package interior. The sheet wraps around a stack of comestible products and maintains the products in a stacked formation. The sheet also retains the comestible products against lateral movement within the sheet. In an embodiment, the plurality of comestible products are releasably attached to the sheet to prevent the comestible products from sliding out of the sheet. In an embodiment, the sheet may be attached to the package interior.
    Type: Grant
    Filed: December 12, 2006
    Date of Patent: April 25, 2017
    Assignee: WM. WRIGLEY JR. COMPANY
    Inventors: Yoichiro Ishikawa, James W. Wolff, Heather L. Fluegel
  • Patent number: 8843866
    Abstract: A design support apparatus calculates a crosstalk noise value when a power line does not run parallel, for each of a plurality of sections. Moreover, the design support apparatus calculates a coefficient Fshield that becomes larger with decrease in the area of the power line included in an area between two signal lines based on a relative positional relationship between the two signal lines and the power line in a section, for each of the plurality of sections. Moreover, the design support apparatus corrects the crosstalk noise value corresponding to a section, using the coefficient Fshield corresponding to the section, for each of the plurality of sections. Moreover, the design support apparatus calculates a total of the corrected crosstalk noise values corresponding respectively to the plurality of sections as a crosstalk noise value between the two signal lines.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: September 23, 2014
    Assignee: Fujitsu Limited
    Inventor: Yoichiro Ishikawa
  • Publication number: 20140157219
    Abstract: A design support apparatus calculates a crosstalk noise value when a power line does not run parallel, for each of a plurality of sections. Moreover, the design support apparatus calculates a coefficient Fshield that becomes larger with decrease in the area of the power line included in an area between two signal lines based on a relative positional relationship between the two signal lines and the power line in a section, for each of the plurality of sections. Moreover, the design support apparatus corrects the crosstalk noise value corresponding to a section, using the coefficient Fshield corresponding to the section, for each of the plurality of sections. Moreover, the design support apparatus calculates a total of the corrected crosstalk noise values corresponding respectively to the plurality of sections as a crosstalk noise value between the two signal lines.
    Type: Application
    Filed: September 26, 2013
    Publication date: June 5, 2014
    Applicant: FUJITSU LIMITED
    Inventor: YOICHIRO ISHIKAWA
  • Patent number: 8713503
    Abstract: A design assisting apparatus includes a memory configured to store routing information representing first wire line from wire lines of a module belonging to a first layer of a semiconductor circuit having a plurality of layers, the first wire line likely to become either one of an aggressor net and a victim net in a crosstalk noise check performed on wire lines of a module belonging to a second layer hierarchically higher than the first layer, and a processor configured to perform a wire line identifying operation identifying second wire line within the module belonging to the second layer, and likely to become either one of an aggressor net and a victim net in the crosstalk noise check performed on the first wire line represented by the routing information stored on the memory.
    Type: Grant
    Filed: November 8, 2011
    Date of Patent: April 29, 2014
    Assignee: Fujitsu Limited
    Inventor: Yoichiro Ishikawa
  • Publication number: 20120124540
    Abstract: A design assisting apparatus includes a memory configured to store routing information representing first wire line from wire lines of a module belonging to a first layer of a semiconductor circuit having a plurality of layers, the first wire line likely to become either one of an aggressor net and a victim net in a crosstalk noise check performed on wire lines of a module belonging to a second layer hierarchically higher than the first layer, and a processor configured to perform a wire line identifying operation identifying second wire line within the module belonging to the second layer, and likely to become either one of an aggressor net and a victim net in the crosstalk noise check performed on the first wire line represented by the routing information stored on the memory.
    Type: Application
    Filed: November 8, 2011
    Publication date: May 17, 2012
    Applicant: FUJITSU LIMITED
    Inventor: Yoichiro ISHIKAWA
  • Patent number: 7962884
    Abstract: The present invention is aimed to efficiently realize a reduction in size of and dead space in a semiconductor integrated circuit while securing freedom of placement and wiring of internal components of placement objects and suppressing an increase of constraints of CAD system. A floorplanning apparatus has a temporary placement section temporarily arranging a plurality of placement object blocks onto a mounting region so that at least two placement object blocks among the plurality of placement object blocks overlap each other to form an overlap region, and an optimization section changing arrangement of the internal components in at least one placement object block among the placement object blocks forming the overlap region while using the overlap region to optimize at least one placement object block.
    Type: Grant
    Filed: December 10, 2007
    Date of Patent: June 14, 2011
    Assignee: Fujitsu Limited
    Inventor: Yoichiro Ishikawa
  • Patent number: 7882466
    Abstract: There is provided a technique in which internal wires of a large cell are spuriously patterned and treated as object of a noise check. Internal wires of a large cell are spuriously determined based on terminal information and wiring forbidden information of the large cell and are added to chip wires to be checked, from which an object wire to be checked and at least one affecting wire are selected, a noise value representing a degree at which the at least one affecting wire induces noise onto the signal of the object wire is calculated and the noise check is performed on the basis of the calculated noise check.
    Type: Grant
    Filed: June 18, 2008
    Date of Patent: February 1, 2011
    Assignee: Fujitsu Limited
    Inventor: Yoichiro Ishikawa
  • Publication number: 20100333054
    Abstract: A circuit design assisting apparatus for assisting a circuit design of a semiconductor by using a noise check result corresponding to a plurality of wiring arrangements, the circuit design assisting apparatus includes a database unit that stores the wiring arrangement data, a wire specifying unit that specifies a first wire from the wiring arrangement data, a wire extracting unit that extracts a plurality of second wires respectively including a wire portion influencing noise to the specified first wire from the wiring arrangement data, and a display controlling unit that generates display information to display the specified first wire and the extracted second wire.
    Type: Application
    Filed: June 14, 2010
    Publication date: December 30, 2010
    Applicant: Fujitsu Limited
    Inventor: Yoichiro ISHIKAWA
  • Publication number: 20100209551
    Abstract: A reclosable package having an opening panel such that when the panel is in a closed position, the confectionery product within the package is retained and when the panel is in an open position, the product is exposed for dispensing. The confectionery product may be oriented in a manner with respect to the opening defined by the opening panel to provide easy access to a consumer.
    Type: Application
    Filed: October 18, 2007
    Publication date: August 19, 2010
    Inventors: Ujjaini Mitra-Shah, James Bougoulas, Yoichiro Ishikawa
  • Patent number: 7493579
    Abstract: In the static noise check of the LSI hierarchical design, in order to reduce the data volume of the common parts and load of the design operation and design automation, when a plurality of cores, comprising same sub-chips, are present, the static noise check data for the whole chip is generated from the core-level design data of one of the cores, and the chip-level design data.
    Type: Grant
    Filed: March 29, 2005
    Date of Patent: February 17, 2009
    Assignee: Fujitsu Limited
    Inventor: Yoichiro Ishikawa
  • Publication number: 20080250366
    Abstract: There is provided a technique in which internal wires of a large cell are spuriously patterned and treated as object of a noise check. Internal wires of a large cell are spuriously determined based on terminal information and wiring forbidden information of the large cell and are added to chip wires to be checked, from which an object wire to be checked and at least one affecting wire are selected, a noise value representing a degree at which the at least one affecting wire induces noise onto the signal of the object wire is calculated and the noise check is performed on the basis of the calculated noise check.
    Type: Application
    Filed: June 18, 2008
    Publication date: October 9, 2008
    Inventor: Yoichiro ISHIKAWA
  • Publication number: 20080127016
    Abstract: The present invention is aimed to efficiently realize a reduction in size of and dead space in a semiconductor integrated circuit while securing freedom of placement and wiring of internal components of placement objects and suppressing an increase of constraints of CAD system. A floorplanning apparatus has a temporary placement section temporarily arranging a plurality of placement object blocks onto a mounting region so that at least two placement object blocks among the plurality of placement object blocks overlap each other to form an overlap region, and an optimization section changing arrangement of the internal components in at least one placement object block among the placement object blocks forming the overlap region while using the overlap region to optimize at least one placement object block.
    Type: Application
    Filed: December 10, 2007
    Publication date: May 29, 2008
    Applicant: FUJITSU LIMITED
    Inventor: Yoichiro ISHIKAWA
  • Patent number: 7325212
    Abstract: Noise related to a part of electronic circuits that are to be designed is computed. If the computed noise exceeds a limiting value, parameters of the electronic circuits are modified by using a predetermined method (simple noise check) so that the noise is less than or equal to the limiting value. Signal transmission timing is analyzed for all the electronic circuits, and noise related to all the electronic circuits whose signal transmission timing is analyzed is computed. If the noise exceeds the limiting value, the simple noise check is executed.
    Type: Grant
    Filed: February 27, 2006
    Date of Patent: January 29, 2008
    Assignee: Fujitsu Limited
    Inventor: Yoichiro Ishikawa
  • Publication number: 20070141199
    Abstract: The present invention provides an improved product holding and dispensing package and an improved method for manufacturing, holding, and storing products, especially comestible products. In an embodiment, a package for comestible products may be provided. The package includes a package blank having walls that define a package interior. The package also includes a sheet disposed inside the package interior. The sheet wraps around a stack of comestible products and maintains the products in a stacked formation. The sheet also retains the comestible products against lateral movement within the sheet. In an embodiment, the plurality of comestible products are releasably attached to the sheet to prevent the comestible products from sliding out of the sheet. In an embodiment, the sheet may be attached to the package interior.
    Type: Application
    Filed: December 12, 2006
    Publication date: June 21, 2007
    Applicant: Wm. Wrigley Jr. Company
    Inventors: Yoichiro Ishikawa, James Wolff, Heather Fluegel
  • Patent number: 7191421
    Abstract: An integrated circuit design apparatus includes a block placement processing unit which performs processing of creation of a lower-rank mounting block in a higher-rank mounting block, and performs processing of creation of virtual placement regions in each of the lower-rank mounting block and the higher-rank mounting block. A functional block assignment processing unit performs processing of assignment of functional blocks to each of the virtual placement regions provided by the block placement processing unit. An evaluation processing unit provides a display of a condition of the functional blocks assigned to each of the virtual placement regions of both the lower-rank mounting block and the higher-rank mounting block, in order to evaluate the condition of the assigned functional blocks.
    Type: Grant
    Filed: March 25, 2002
    Date of Patent: March 13, 2007
    Assignee: Fujitsu Limited
    Inventors: Yasuo Amano, Hiroshi Seki, Yukio Makino, Yumiko Yamanishi, Yoshiko Nakanishi, Yoichiro Ishikawa
  • Patent number: 7158920
    Abstract: The apparatus reduces the amount of correction for noise value error, so as to reduce work needed for correction to ensure error avoidance, and to improve the freedom of layout design, and to reduce load on DA. Based on a timing chart of signal transfer on each wire, the last edge appearance timing in the signal waveform of a victim whose noise value exceeds a limit value is compared with the last edge appearance timing in the signal waveform of an aggressor, to evaluate the noise value error in the victim. The apparatus is used in static noise checking of cell arrangement and inter-cell wiring after such cell arrangement and inter-cell wiring are performed at design of integrated circuits such as LSIs.
    Type: Grant
    Filed: November 3, 2004
    Date of Patent: January 2, 2007
    Assignee: Fujitsu Limited
    Inventor: Yoichiro Ishikawa
  • Patent number: D729058
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: May 12, 2015
    Assignee: WM. Wrigley Jr. Company
    Inventor: Yoichiro Ishikawa
  • Patent number: D739229
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: September 22, 2015
    Assignee: WM. WRIGLEY JR. COMPANY
    Inventors: Jan Kusper, Yoichiro Ishikawa