Patents by Inventor Yoichiro Kurita

Yoichiro Kurita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10658338
    Abstract: According to one embodiment, a semiconductor device includes a re-interconnection layer, bumps, chips, and a resin member. The bumps are provided on a first surface of the re-interconnection layer. The chips are stacked on a second surface of the re-interconnection layer. The resin member is provided on the second surface, and covers the chips. The re-interconnection layer includes an insulating layer, an interconnection, a first via, an electrode layer, and a second via. The interconnection is provided in the insulating layer. The first via is provided in the insulating layer and connected to the interconnection. The electrode layer is provided in the insulating layer, formed of a metal material different from a material of the first via, exposed on the first surface, and connected to the first via and the bumps. The second via is provided in the insulating layer, and connected to the interconnection and the chips.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: May 19, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takayuki Tajima, Yoichiro Kurita, Kazuo Shimokawa
  • Publication number: 20200118994
    Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.
    Type: Application
    Filed: December 10, 2019
    Publication date: April 16, 2020
    Inventors: Yoichiro KURITA, Masaya KAWANO, Koji SOEJIMA
  • Patent number: 10580763
    Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: March 3, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Yoichiro Kurita, Masaya Kawano, Koji Soejima
  • Patent number: 10566219
    Abstract: According to one embodiment, a chip transfer member includes a light-transmitting portion and a metal portion. The light-transmitting portion has a light incident surface, a light-emitting surface, and a side surface. The metal portion is provided at the side surface of the light-transmitting portion.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: February 18, 2020
    Assignee: TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Yoichiro Kurita, Tomoyuki Abe, Hideto Furuyama
  • Publication number: 20200051953
    Abstract: A bonding method of a first member includes arranging an activated front surface of a first member and an activated front surface of a second member so as to face each other with a back surface of the first member attached to a sheet, pushing a back surface of the first member through the sheet to closely attach the activated front surface of the first member and the activated front surface of the second member, and stripping the sheet from the back surface of the first member while maintaining a state in which the activated front surface of the first member is closely attached to the activated front surface of the second member.
    Type: Application
    Filed: October 18, 2019
    Publication date: February 13, 2020
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Yoichiro KURITA
  • Publication number: 20200035646
    Abstract: According to one embodiment, the interconnect layer includes a fourth conductive member and a fifth conductive member. The fourth conductive member is provided between the first region of the first chip and the third region of the second chip. The fourth conductive member connects the first conductive member of the first chip and the second conductive member of the second chip. The fifth conductive member is provided between the second region of the first chip and the fifth region of the third chip. The fifth conductive member connects the first conductive member of the first chip and the third conductive member of the third chip. The first chip is provided between the first terminal and the second terminal.
    Type: Application
    Filed: October 3, 2019
    Publication date: January 30, 2020
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Yoichiro KURITA
  • Patent number: 10510725
    Abstract: A semiconductor device includes a base member having a first surface and a second surface on a side opposite to the first surface, the base member including at least one interconnect extending in a first direction along the first surface; two or more stacked bodies arranged in the first direction on the first surface, each of the two or more stacked bodies including semiconductor chips stacked in a second direction perpendicular to the first surface; and logic chips electrically connected respectively to the stacked bodies. Each of semiconductor chips includes first and second semiconductor layers. The first and second semiconductor layers each have an element surface and a back surface. An active element is provided on the element surface. The first semiconductor layer and the second semiconductor layer are bonded such that the element surface of the second semiconductor layer faces the element surface of the first semiconductor layer.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: December 17, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Kazushige Kawasaki, Yoichiro Kurita
  • Patent number: 10497688
    Abstract: A semiconductor device according to an embodiment includes a first memory chip having a first front surface and a first back surface and having a first memory circuit provided on the first front surface side; a second memory chip having a second front surface and a second back surface facing the first front surface, having a second memory circuit provided on the second front surface side, and being electrically connected to the first memory chip; and a logic chip having the first memory chip provided between the logic chip and the second memory chip, having a third front surface and a third back surface, having a logic circuit provided on the third front surface side, and being electrically connected to the first memory chip.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: December 3, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Satoshi Tsukiyama, Yoichiro Kurita, Hideo Aoki, Kazushige Kawasaki
  • Patent number: 10475767
    Abstract: According to one embodiment, the interconnect layer includes a fourth conductive member and a fifth conductive member. The fourth conductive member is provided between the first region of the first chip and the third region of the second chip. The fourth conductive member connects the first conductive member of the first chip and the second conductive member of the second chip. The fifth conductive member is provided between the second region of the first chip and the fifth region of the third chip. The fifth conductive member connects the first conductive member of the first chip and the third conductive member of the third chip. The first chip is provided between the first terminal and the second terminal.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: November 12, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoichiro Kurita
  • Patent number: 10429598
    Abstract: According to one embodiment, an optical device includes an optical element and a via. The optical element is provided directly on a second main surface opposed to a first main surface of a semiconductor substrate. The via is aligned with the optical element and formed to extend halfway in a thickness direction from the first main surface of the semiconductor substrate.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: October 1, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoichiro Kurita, Hideto Furuyama, Hiroshi Uemura, Fumitaka Ishibashi
  • Publication number: 20190285814
    Abstract: According to one embodiment, the silicon substrate includes a thinned portion and a side wall provided around the thinned portion. The thinned portion is thinned selectively from one surface. The optical element is formed on a surface of the thinned portion. The surface of the thinned portion is opposite to the one surface of the silicon substrate. The light guide member includes a lens portion, a light guide portion, and an alignment portion. The light guide portion is provided between the lens portion and the optical element. The alignment portion is for an optical connector. The thinned portion of the silicon substrate is provided between the light guide portion of the light guide member and the optical element.
    Type: Application
    Filed: August 31, 2018
    Publication date: September 19, 2019
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hideto FURUYAMA, Yoichiro KURITA, Hiroshi UEMURA
  • Publication number: 20190267350
    Abstract: According to one embodiment, a semiconductor device includes a re-interconnection layer, bumps, chips, and a resin member. The bumps are provided on a first surface of the re-interconnection layer. The chips are stacked on a second surface of the re-interconnection layer. The resin member is provided on the second surface, and covers the chips. The re-interconnection layer includes an insulating layer, an interconnection, a first via, an electrode layer, and a second via. The interconnection is provided in the insulating layer. The first via is provided in the insulating layer and connected to the interconnection. The electrode layer is provided in the insulating layer, formed of a metal material different from a material of the first via, exposed on the first surface, and connected to the first via and the bumps. The second via is provided in the insulating layer, and connected to the interconnection and the chips.
    Type: Application
    Filed: August 8, 2018
    Publication date: August 29, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Takayuki TAJIMA, Yoichiro KURITA, Kazuo SHIMOKAWA
  • Patent number: 10396060
    Abstract: According to one embodiment, a semiconductor device includes an interconnect layer, an electrical element, an optical element, and a resin portion. The resin portion includes a first partial region between the electrical element and the optical element. At least a portion of the optical element does not overlap the resin portion in a first direction. The first partial region has first and second resin portion surfaces. The second resin portion surface is opposite to the first resin portion surface and opposes the interconnect layer. The optical element has first and second optical element surfaces. The second optical element surface is opposite to the first optical element surface and opposes the interconnect layer. A distance along the first direction between the interconnect layer and the first resin portion surface is longer than a distance along the first direction between the interconnect layer and the first optical element surface.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: August 27, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoichiro Kurita, Hideto Furuyama, Hiroshi Uemura
  • Publication number: 20190252219
    Abstract: According to one embodiment, a chip transfer member includes a light-transmitting portion and a metal portion. The light-transmitting portion has a light incident surface, a light-emitting surface, and a side surface. The metal portion is provided at the side surface of the light-transmitting portion.
    Type: Application
    Filed: September 12, 2018
    Publication date: August 15, 2019
    Applicants: TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION, AYUMI INDUSTRIES COMPANY LIMITED
    Inventors: Yoichiro KURITA, Tomoyuki ABE, Hideto FURUYAMA
  • Patent number: 10373929
    Abstract: A method of manufacturing a semiconductor device includes forming an insulation layer on a support body, selectively forming openings through the insulation layer, forming a conductor pattern in the openings, and above selected portions of, the insulation layer, mounting a first semiconductor element on the insulation layer and electrically connecting the first semiconductor element to the conductor pattern, forming a resin over the first semiconductor element and the insulation layer, removing the support body after the resin is formed to expose a surface of a portion of the conductor pattern, etching the exposed surface of the portion of the conductor pattern to form a recess over the portion of the conductor pattern, and forming a pad containing a metal different than the metal of the conductor pattern in the recess in contact with the conductor pattern.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: August 6, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yoichiro Kurita
  • Publication number: 20190229104
    Abstract: The semiconductor device 100 comprises a first semiconductor element 113 provided on a face on one side of a flat plate shaped interconnect component 101, an insulating resin 119 covering a face of a side where the first semiconductor element 113 of the interconnect component 101 is provided and a side face of the first semiconductor element 113, and a second semiconductor element 111 provided on a face on the other side of the interconnect component 101. The interconnect component 101 has a constitution where an interconnect layer 103, a silicon layer 105 and an insulating film 107 are sequentially formed. The interconnect layer 103 has a constitution where the interconnect layer 103 has a flat plate shaped insulating component and a conductive component extending through the insulating component. The first semiconductor element 113 is electrically connected with the second semiconductor element 111 through the conductive component.
    Type: Application
    Filed: April 4, 2019
    Publication date: July 25, 2019
    Inventor: Yoichiro KURITA
  • Publication number: 20190206837
    Abstract: According to one embodiment, the interconnect layer includes a fourth conductive member and a fifth conductive member. The fourth conductive member is provided between the first region of the first chip and the third region of the second chip. The fourth conductive member connects the first conductive member of the first chip and the second conductive member of the second chip. The fifth conductive member is provided between the second region of the first chip and the fifth region of the third chip. The fifth conductive member connects the first conductive member of the first chip and the third conductive member of the third chip. The first chip is provided between the first terminal and the second terminal.
    Type: Application
    Filed: July 6, 2018
    Publication date: July 4, 2019
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Yoichiro KURITA
  • Publication number: 20190157252
    Abstract: According to one embodiment, a semiconductor device includes an interconnect layer, an electrical element, an optical element, and a resin portion. The resin portion includes a first partial region between the electrical element and the optical element. At least a portion of the optical element does not overlap the resin portion in a first direction. The first partial region has first and second resin portion surfaces. The second resin portion surface is opposite to the first resin portion surface and opposes the interconnect layer. The optical element has first and second optical element surfaces. The second optical element surface is opposite to the first optical element surface and opposes the interconnect layer. A distance along the first direction between the interconnect layer and the first resin portion surface is longer than a distance along the first direction between the interconnect layer and the first optical element surface.
    Type: Application
    Filed: February 23, 2018
    Publication date: May 23, 2019
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoichiro KURITA, Hideto FURUYAMA, Hiroshi UEMURA
  • Publication number: 20190139953
    Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.
    Type: Application
    Filed: January 3, 2019
    Publication date: May 9, 2019
    Inventors: Yoichiro KURITA, Masaya KAWANO, Koji SOEJIMA
  • Publication number: 20190088634
    Abstract: A semiconductor device according to an embodiment includes a first memory chip having a first front surface and a first back surface and having a first memory circuit provided on the first front surface side; a second memory chip having a second front surface and a second back surface facing the first front surface, having a second memory circuit provided on the second front surface side, and being electrically connected to the first memory chip; and a logic chip having the first memory chip provided between the logic chip and the second memory chip, having a third front surface and a third back surface, having a logic circuit provided on the third front surface side, and being electrically connected to the first memory chip.
    Type: Application
    Filed: March 20, 2018
    Publication date: March 21, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Satoshi TSUKIYAMA, Yoichiro Kurita, Hideo Aoki, Kazushige Kawasaki