Abstract: The present disclosure relates to an integrated chip comprising a substrate having a first pair of opposing sidewalls that define a trench. The trench extends into a front-side surface of the substrate. A first source/drain region is disposed along the front-side surface of the substrate. A second source/drain region is disposed along the front-side surface of the substrate. A gate structure is disposed within the trench and is arranged laterally between the first source/drain region and the second source/drain region. The gate structure extends along the first pair of opposing sidewalls to an upper surface of the substrate. A bottom surface of the gate structure is disposed below a bottom surface of the first source/drain region.

Abstract: An energy storage device includes a sensor, a communication circuit and a processor. The sensor is configured to detect an abnormal event occurred in the energy storage device. The communication circuit is configured to connect to a local area network. The local area network includes a plurality of nodes formed by the energy storage device and other energy storage devices. The processor is configured to generate, according to the abnormal event detected by the sensor, historical usage data recording the abnormal event. In response to a trigger event, the processor is further configured to: update the historical usage data; and control the communication circuit to transmit at least part of the updated historical usage data to at least one energy storage device adjacent to the energy storage device in the local area network.

Abstract: A device includes an active region, a select gate, a control gate, a first metal alloy layer, and a second metal alloy layer. The active region has a source region and a drain region. The select gate is over the active region and between the source region and the drain region. The control gate is over the active region and between the source region and the select gate. The first metal alloy layer is in contact with the source region. The second metal alloy layer is in contact with the drain region and higher than a top surface of the control gate.

Abstract: Various embodiments of the present disclosure are directed towards a method for opening a source line in a memory device. An erase gate line (EGL) and the source line are formed elongated in parallel. The source line underlies the EGL and is separated from the EGL by a dielectric layer. A first etch is performed to form a first opening through the EGL and stops on the dielectric layer. A second etch is performed to thin the dielectric layer at the first opening, wherein the first and second etches are performed with a common mask in place. A silicide process is performed to form a silicide layer on the source line at the first opening, wherein the silicide process comprises a third etch with a second mask in place and extends the first opening through the dielectric layer. A via is formed extending through the EGL to the silicide layer.

Abstract: A convolution operation method includes: configuring an operation apparatus according to a partition rule; reading an operation data partition; reading a depthwise convolution parameter partition to perform a depthwise weighting operation to generate a depthwise weighted partition; performing a depthwise offset operation to generate a depthwise convolution operation result partition; reading a pointwise convolution parameter partition to perform a pointwise weighting operation on the depthwise convolution operation result partition to generate a pointwise weighted partition, and performing an accumulation process in a depth dimension to generate an output partition; when the output partition meets operation criteria in the depth dimension, performing a pointwise offset operation on the output partition to generate and output a pointwise convolution operation result partition; and when the output partition does not meet the operation criteria in the depth dimension, configuring the output partition to be a pre

Abstract: The present disclosure relates to an integrated chip comprising a substrate having a first pair of opposing sidewalls that define a trench. The trench extends into a front-side surface of the substrate. A first source/drain region is disposed along the front-side surface of the substrate. A second source/drain region is disposed along the front-side surface of the substrate. A gate structure is disposed within the trench and is arranged laterally between the first source/drain region and the second source/drain region. The gate structure extends along the first pair of opposing sidewalls to an upper surface of the substrate. A bottom surface of the gate structure is disposed below a bottom surface of the first source/drain region.

Abstract: Various embodiments of the present disclosure are directed towards a method for opening a source line in a memory device. An erase gate line (EGL) and the source line are formed elongated in parallel. The source line underlies the EGL and is separated from the EGL by a dielectric layer. A first etch is performed to form a first opening through the EGL and stops on the dielectric layer. A second etch is performed to thin the dielectric layer at the first opening, wherein the first and second etches are performed with a common mask in place. A silicide process is performed to form a silicide layer on the source line at the first opening, wherein the silicide process comprises a third etch with a second mask in place and extends the first opening through the dielectric layer. A via is formed extending through the EGL to the silicide layer.

Abstract: There is provided a method of synthesizing a porous carbon-sulfur composite comprising the step of carbonizing a carbon material having a metal-organic framework (MOF) at a temperature of 800-1000° C. to produce a porous carbon, mixing and heating the porous carbon with sulfur to infuse the sulfur (melt diffusion) into the pores of the porous carbon and removing excess sulfur not infused into the pores or present on the surface of the porous carbon. There is also provided a cathode comprising the porous carbon-sulfur composite and a method of preparing the cathode by mixing with conductive carbon and a polymer binder. The cathode finds use in an electrochemical cell comprising a sodium or lithium anode.

Abstract: A method (400) of capturing and processing electroluminescence (EL) images (1910) of a PV array (40) is disclosed herein.

Abstract: A memory device includes an active region, a select gate, a control gate, and a blocking layer. The active region includes a bottom portion and a protruding portion protruding from the bottom portion. A source is in the bottom portion and a drain is in the protruding portion. The select gate is above the bottom portion. A top surface of the select gate is lower than a top surface of the protruding portion. The control gate is above the bottom portion. The blocking layer is between the select gate and the control gate.

Abstract: A distance determination method has: detecting a first received signal strength indicator (RSSI) of a first electronic device by a second electronic device; detecting a second RSSI of the second electronic device by the first electronic device; obtaining the first RSSI from the second electronic device by the first electronic device; and calculating a motion direction and a distance of the second electronic device relative to the first electronic device according to the first RSSI and the second RSSI by the first electronic device.

Abstract: The present disclosure relates to an integrated chip comprising a substrate having a first top surface disposed at a first height, a second top surface disposed at a second height that is less than the first height, and a connecting surface extending from the first top surface to the second top surface. A first source/drain region is disposed along the first top surface of the substrate. A second source/drain region is disposed along the second top surface of the substrate and is laterally separated from the first source/drain region by a channel region of the substrate. A gate structure is arranged between the first source/drain region and the second source/drain region. The gate structure extends from over the first top surface of the substrate to over the connecting surface of the substrate. The gate structure also extends below the first top surface of the substrate.

Abstract: There is provided a composite comprising a) a short chain sulfur; and b) a carbon-supported conductive polymer such as polyacrylonitrile, wherein sulfur atoms of said short chain sulfur are covalently linked to the conductive polymer of said carbon-supported conductive polymer via a C—S bond. A method of preparing said composite comprising polymerizing a plurality of monomers in the presence of a carbon scaffold, mixing elemental sulfur and heating the mixture to obtain said composite is also disclosed. An electrochemical cell comprising said composite as cathode, a sodium anode and a liquid electrolyte such as sodium trifluoromethanesulfonate dissolved in a mixture of solvents is disclosed.

Abstract: A memory device and a manufacturing method are provided. The method includes: forming a first conductive pattern on a substrate; forming an active structure over the first conductive pattern, wherein the active structure comprises a gate pattern, a channel pillar and a charge storage layer, the channel pillar penetrates the gate pattern and electrically connects with the first conductive pattern, and the charge storage layer is disposed between the gate pattern and the channel pillar; forming a second conductive pattern over the active structure, wherein the second conductive pattern is electrically connected with the channel pillar; and performing formation of the active structure one more time, such that the channel pillars of the active structures are vertically spaced apart from each other, and electrically connected to the second conductive pattern extending in between the channel pillars.

Abstract: Embodiments are described for a system and method to analyze data at a plurality of data sources. A data analytic workflow may be received. The data analytic workflow may include at least one operation to be performed on a plurality of data sets stored at a plurality of data sources. Instructions may be created based on the operation to be performed and a type of platform that operates the data sources. Furthermore, the instructions may be transmitted to the data sources such that the data sources may execute the operations on the data sets stored at the data sources.

Abstract: A carbonized composite comprising a sulfur chain and a conductive network, wherein said sulfur chain is covalently bonded to said conductive network via one or more C—S bonds. The present disclosure also provides a method of preparing the carbonized composite disclosed herein. The carbonized composite may be used in electrochemical cells comprising a reactive metal anode.

Abstract: The present disclosure relates to an integrated chip comprising a substrate having a first top surface disposed at a first height, a second top surface disposed at a second height that is less than the first height, and a connecting surface extending from the first top surface to the second top surface. A first source/drain region is disposed along the first top surface of the substrate. A second source/drain region is disposed along the second top surface of the substrate and is laterally separated from the first source/drain region by a channel region of the substrate. A gate structure is arranged between the first source/drain region and the second source/drain region. The gate structure extends from over the first top surface of the substrate to over the connecting surface of the substrate. The gate structure also extends below the first top surface of the substrate.

Abstract: The present disclosure relates to an integrated chip comprising a substrate having a first top surface disposed at a first height, a second top surface disposed at a second height that is less than the first height, and a connecting surface extending from the first top surface to the second top surface. A first source/drain region is disposed along the first top surface of the substrate. A second source/drain region is disposed along the second top surface of the substrate and is laterally separated from the first source/drain region by a channel region of the substrate. A gate structure is arranged between the first source/drain region and the second source/drain region. The gate structure extends from over the first top surface of the substrate to over the connecting surface of the substrate. The gate structure also extends below the first top surface of the substrate.

Abstract: Various embodiments of the present disclosure are directed towards a method for opening a source line in a memory device. An erase gate line (EGL) and the source line are formed elongated in parallel. The source line underlies the EGL and is separated from the EGL by a dielectric layer. A first etch is performed to form a first opening through the EGL and stops on the dielectric layer. A second etch is performed to thin the dielectric layer at the first opening, wherein the first and second etches are performed with a common mask in place. A silicide process is performed to form a silicide layer on the source line at the first opening, wherein the silicide process comprises a third etch with a second mask in place and extends the first opening through the dielectric layer. A via is formed extending through the EGL to the silicide layer.

Abstract: The present disclosure provides a server baseboard, relates to the field of computer technology and can be applied to the fields of cloud computing and big data. A specific implementation scheme is that the server baseboard includes: a main control program module, a switch chip connected to the main control program module, and a plurality of physical network ports for connecting the switch chip to a management network and a baseboard other than the baseboard where the main control program module is located. The server baseboard can reduce the construction cost of the management network, and improve the availability of a server and the security of a service network. The present disclosure also provides a server, a control method, an electronic apparatus, and a readable medium.