Patents by Inventor Yong Woo Lee

Yong Woo Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory system
    Patent number: 9990143
    Abstract: A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (OS) and an application, and accessing data storage memory through the first and second memory devices.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: June 5, 2018
    Assignee: SK Hynix Inc.
    Inventors: Do-Yun Lee, Min-Chang Kim, Chang-Hyun Kim, Yong-Woo Lee, Jae-Jin Lee, Hoe-Kwon Jung
  • Memory system
    Patent number: 9990283
    Abstract: A memory system includes: a first memory device including a plurality of first memories and a first memory controller suitable for controlling the plurality of first memories to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (OS) and an application to access a data storage memory through the first and second memory devices.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: June 5, 2018
    Assignee: SK Hynix Inc.
    Inventors: Do-Yun Lee, Min-Chang Kim, Chang-Hyun Kim, Yong-Woo Lee, Jae-Jin Lee, Hoe-Kwon Jung
  • Memory system
    Patent number: 9977606
    Abstract: A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (OS) and an application to access a data storage memory through the first and second memory devices.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: May 22, 2018
    Assignee: SK Hynix Inc.
    Inventors: Min-Chang Kim, Chang-Hyun Kim, Do-Yun Lee, Yong-Woo Lee, Jae-Jin Lee, Hoe-Kwon Jung
  • METHOD AND DEVICE FOR GENERATING DRIVING ASSISTANCE INFORMATION
    Publication number: 20180134215
    Abstract: A method of generating running assistance information includes recognizing a running pattern of a vehicle based on information about a current state of the vehicle which is sensed while the vehicle is running; determining a current status of a driver of the vehicle based on the running pattern of the vehicle; and generating a notification signal based on a risk level of the driver determined based on the determined current status of the driver.
    Type: Application
    Filed: September 8, 2017
    Publication date: May 17, 2018
    Inventors: Gye-hyun KIM, Tae-hyeong KIM, Chee-hoon LEE, Yong-woo LEE
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20180082892
    Abstract: Provided herein is a method of manufacturing a semiconductor device. The method may include forming an amorphous channel layer. The method may include forming a diffusion barrier on the amorphous channel layer. The method may include forming an amorphous seed layer on the diffusion barrier. The method may include forming a seed layer by crystallizing the amorphous seed layer. The method may include forming a channel layer by crystallizing the amorphous channel layer.
    Type: Application
    Filed: March 23, 2017
    Publication date: March 22, 2018
    Applicant: SK hynix Inc.
    Inventors: Yong Woo LEE, Jin Ha KIM
  • ELECTRONIC APPARATUS AND RECORDING MEDIUM
    Publication number: 20180061369
    Abstract: An electronic apparatus of the present disclosure includes: a communicator comprising communication circuitry configured to wirelessly communicate with one or more external apparatuses; a signal processor configured to process data; and a controller configured to control an external apparatus to be designated as a transmitter for transmitting data and the electronic apparatus to be designated as a receiver for receiving the data from the transmitter if it is determined that the external apparatus is within a preset distance of the electronic apparatus and the external apparatus is moving.
    Type: Application
    Filed: June 28, 2017
    Publication date: March 1, 2018
    Inventors: Yong-woo LEE, Chang-heon YOON
  • Memory device and system including the same
    Patent number: 9886992
    Abstract: A memory device may include: an active controller configured to output a row active signal in response to a refresh control signal and a row enable signal when an active signal is activated; a refresh controller configured to generate and store a flag bit for controlling a refresh operation in response to a refresh signal, a precharge signal, and a precharge stop signal, and output the row enable signal corresponding to the stored flag bit to the active controller; and a cell array circuit configured to perform a refresh operation in memory cell array areas in response to the row active signal.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: February 6, 2018
    Assignee: SK hynix Inc.
    Inventors: Chang Hyun Kim, Min Chang Kim, Do Yun Lee, Yong Woo Lee, Jae Jin Lee, Hun Sam Jung, Hoe Kwon Jung
  • Test apparatus, test system and operating method of test apparatus
    Patent number: 9831001
    Abstract: A test system may include: a vector storage unit suitable for storing a first test vector corresponding to a first test operation; a test target suitable for performing a test operation corresponding to the test vector stored in a vector storage unit; a comparison unit suitable for comparing a first test result to an expected value to output a first test result value, wherein the first test result is transferred from the test target as a result of the first test operation based on the first test vector; and a vector control unit suitable for modifying the first test vector to generate a second test vector corresponding to a second test operation.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: November 28, 2017
    Assignee: SK Hynix Inc.
    Inventor: Yong-Woo Lee
  • Semiconductor device and method of fabricating the same
    Patent number: 9818825
    Abstract: A method of fabricating a semiconductor device is provided as follows. A channel layer is formed on a strain relaxed buffer (SRB) layer. A first etching process is performed on the channel layer and the SRB layer to form a plurality of trenches. The trenches penetrate through the channel layer and into the SRB layer to a first depth. First liners are formed on first sidewalls of the trenches having the first depth. The first liners cover the first sidewalls. A second etching process is performed on the SRB layer exposed through the trenches. The second etching process is performed on the SRB layer using a gas etchant having etch selectivity with respect to the first liners so that after the performing of the second etching process, the first liners remain on the first sidewalls.
    Type: Grant
    Filed: May 3, 2016
    Date of Patent: November 14, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-Kwon Kim, Yong-Woo Lee
  • LIQUID CRYSTAL DISPLAY DEVICE
    Publication number: 20170322468
    Abstract: A liquid crystal display device includes a substrate, a first coupling electrode disposed on the substrate, a first insulating layer disposed on the first coupling electrode, a second coupling electrode disposed on the first insulating layer and capacitively coupled to the first coupling electrode, a second insulating layer disposed on the second coupling electrode, and a pixel electrode including first and second sub-pixel electrodes, which are disposed on the second insulating layer and are electrically insulated from each other, where the first sub-pixel electrode is electrically connected to the first coupling electrode via a first contact hole, which is defined in the first and second insulating layers, and the second sub-pixel electrode is electrically connected to the second coupling electrode via a second contact hole which is defined in the second insulating layer.
    Type: Application
    Filed: November 8, 2016
    Publication date: November 9, 2017
    Inventors: Il Joo KIM, Cheol Gon LEE, Gun Woo YANG, Hyun Young CHOI, Tae Ho KANG, Chol Ho KIM, Hae Ryeong PARK, Dong Il YOO, Yong Woo LEE, Mee Hye JUNG, Joong Gun CHONG
  • Memory system
    Patent number: 9786389
    Abstract: A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (OS) and an application, and accessing data storage memory through the first and second memory devices.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: October 10, 2017
    Assignee: SK Hynix Inc.
    Inventors: Hoe-Kwon Jung, Min-Chang Kim, Chang-Hyun Kim, Do-Yun Lee, Yong-Woo Lee, Jae-Jin Lee
  • Display apparatus
    Patent number: 9753314
    Abstract: A display apparatus includes a display panel configured to display an image, a lower receiving container comprising a bottom portion and a side wall and accommodating the display panel and a mold frame integrally formed with the lower receiving container, extending along the side wall of the lower receiving container, and comprising a plurality of groove portions extending from an inner surface of the mold frame toward an outer surface of the mold frame.
    Type: Grant
    Filed: August 13, 2014
    Date of Patent: September 5, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Won-Seok Kim, Toru Tsunekawa, Yong-Woo Lee
  • MEMORY DEVICE AND SYSTEM INCLUDING THE SAME
    Publication number: 20170221545
    Abstract: A memory device may include: an active controller configured to output a row active signal in response to a refresh control signal and a row enable signal when an active signal is activated; a refresh controller configured to generate and store a flag bit for controlling a refresh operation in response to a refresh signal, a precharge signal, and a precharge stop signal, and output the row enable signal corresponding to the stored flag bit to the active controller; and a cell array circuit configured to perform a refresh operation in memory cell array areas in response to the row active signal.
    Type: Application
    Filed: April 12, 2017
    Publication date: August 3, 2017
    Applicant: SK hynix Inc.
    Inventors: Chang Hyun KIM, Min Chang KIM, Do Yun LEE, Yong Woo LEE, Jae Jin LEE, Hun Sam JUNG, Hoe Kwon JUNG
  • DISPLAY APPARATUS
    Publication number: 20170139259
    Abstract: A display apparatus includes a display panel configured to display an image, a lower receiving container comprising a bottom portion and a side wall and accommodating the display panel and a mold frame integrally formed with the lower receiving container, extending along the side wall of the lower receiving container, and comprising a plurality of groove portions extending from an inner surface of the mold frame toward an outer surface of the mold frame.
    Type: Application
    Filed: January 26, 2017
    Publication date: May 18, 2017
    Inventors: Won-Seok KIM, Toru TSUNEKAWA, Yong-Woo LEE
  • Structure for mounting rear camera for vehicle
    Patent number: 9649991
    Abstract: A structure for mounting a rear camera for a vehicle, may include a rear glass in which a mounting hole is perforated; a camera housing in which a camera module is embedded; and a wiper pivot which enters the mounting hole from an internal side of the rear glass, and has an end of an external side coupled with a wiper blade, in which the camera housing is mounted so that the wiper pivot passes through the camera housing, and is fixed between the wiper blade and the rear glass, in a manner that the camera housing is coupled so that the wiper pivot passes through an upper portion of the camera housing, and a camera module is located at a lower portion of the camera housing.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: May 16, 2017
    Assignees: Hyundai Motor Company, Kia Motor Corporation
    Inventors: Yong-Hun Lee, Soo-Kyoung Yang, Yong Lee, Sang-Sul Lee, Tae-Yub Kim, Ju-Yong Park, Yun-Seok Oh, Yong-Woo Lee
  • Memory device and system including the same
    Patent number: 9653140
    Abstract: A memory device may include: an active controller configured to output a row active signal in response to a refresh control signal and a row enable signal when an active signal is activated; a refresh controller configured to generate and store a flag bit for controlling a refresh operation in response to a refresh signal, a precharge signal, and a precharge stop signal, and output the row enable signal corresponding to the stored flag bit to the active controller; and a cell array circuit configured to perform a refresh operation in memory cell array areas in response to the row active signal.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: May 16, 2017
    Assignee: SK hynix Inc.
    Inventors: Chang Hyun Kim, Min Chang Kim, Do Yun Lee, Yong Woo Lee, Jae Jin Lee, Hun Sam Jung, Hoe Kwon Jung
  • SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    Publication number: 20170117363
    Abstract: A method of fabricating a semiconductor device is provided as follows. A channel layer is formed on a strain relaxed buffer (SRB) layer. A first etching process is performed on the channel layer and the SRB layer to form a plurality of trenches. The trenches penetrate through the channel layer and into the SRB layer to a first depth. First liners are formed on first sidewalls of the trenches having the first depth. The first liners cover the first sidewalls. A second etching process is performed on the SRB layer exposed through the trenches. The second etching process is performed on the SRB layer using a gas etchant having etch selectivity with respect to the first liners so that after the performing of the second etching process, the first liners remain on the first sidewalls.
    Type: Application
    Filed: May 3, 2016
    Publication date: April 27, 2017
    Inventors: DONG-KWON KIM, YONG-WOO LEE
  • MEMORY SYSTEM
    Publication number: 20170109086
    Abstract: A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (OS) and an application to access a data storage memory through the first and second memory devices.
    Type: Application
    Filed: October 13, 2016
    Publication date: April 20, 2017
    Inventors: Min-Chang KIM, Chang-Hyun KIM, Do-Yun LEE, Yong-Woo LEE, Jae-Jin LEE, Hoe-Kwon JUNG
  • MEMORY SYSTEM
    Publication number: 20170109069
    Abstract: A memory system includes: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (OS) and an application to access a data storage memory through the first and second memory devices.
    Type: Application
    Filed: October 13, 2016
    Publication date: April 20, 2017
    Inventors: Min-Chang KIM, Chang-Hyun KIM, Do-Yun LEE, Yong-Woo LEE, Jae-Jin LEE, Hoe-Kwon JUNG
  • MEMORY DEVICE AND SYSTEM INCLUDING THE SAME
    Publication number: 20170110176
    Abstract: A memory device may include: an active controller configured to output a row active signal in response to a refresh control signal and a row enable signal when an active signal is activated; a refresh controller configured to generate and store a flag bit for controlling a refresh operation in response to a refresh signal, a precharge signal, and a precharge stop signal, and output the row enable signal corresponding to the stored flag bit to the active controller; and a cell array circuit configured to perform a refresh operation in memory cell array areas in response to the row active signal.
    Type: Application
    Filed: March 2, 2016
    Publication date: April 20, 2017
    Inventors: Chang Hyun KIM, Min Chang KIM, Do Yun LEE, Yong Woo LEE, Jae Jin LEE, Hun Sam JUNG, Hoe Kwon JUNG