Abstract: The disclosure relates to bifunctional KRAS-G12D-modulating compounds having the structure W-L-T, where W is a targeting group that binds specifically to KRAS-G12D protein, T is an E3-ligase binding group, and L is absent or is a bivalent linking group that connects W and T together via a covalent linkage. Compounds and pharmaceutical compositions thereof can promote degradation of the KRAS-G12D protein in a cell and are thus useful for treating, inhibiting, and preventing KRAS-G12D-associated diseases, disorders and conditions, including cancers.

Abstract: This application discloses a method for making an elevated source-drain structure of a PMOS in an FDSOI process, including: Step 1, forming a gate structure of a PMOS on an FDSOI substrate; Step 2, forming an elevated source-drain structure, further including: Step 21, forming a seed layer; Step 22, forming a bulk layer, the bulk layer being a B-Ge-doped Si epitaxial layer. Step 23, forming a first cap layer and a second cap layer in sequence, the first cap layer being a B-doped Si epitaxial layer, the second cap layer being a Si epitaxial layer; Step 24, performing a thermal oxidation process to form a top oxide layer and diffuse B impurities from the first cap layer into the bulk layer, the seed layer and the bottom semiconductor substrate; Step 25, removing the top oxide layer; and Step 26, forming a third cap layer.

Abstract: The disclosure relates to bifunctional KRAS-G12D-modulating compounds having the structure W-L-T, where W is a targeting group that binds specifically to KRAS-G12D protein, T is an E3-ligase binding group, and L is absent or is a bivalent linking group that connects W and T together via a covalent linkage. Compounds and pharmaceutical compositions thereof can promote degradation of the KRAS-G12D protein in a cell and are thus useful for treating, inhibiting, and preventing KRAS-G12D-associated diseases, disorders and conditions, including cancers.

Abstract: The present application discloses a method for manufacturing an isolation structure of a hybrid epitaxial area and an active area in an FDSOI, comprising: step 1, providing an FDSOI substrate structure and forming a hard mask layer; step 2, removing the hard mask layer and a semiconductor top layer in the hybrid epitaxial area, so as to form a top trench; step 3, performing lateral etching on the exposed semiconductor top layer from a side surface of the top trench to form a recess cavity; step 4, filling the recess cavity to form an inner spacer; step 5, performing an etching process to form a bottom trench having a bottom surface that exposes a semiconductor body layer; and step 6, performing epitaxial growth to form a semiconductor epitaxial layer in the trench that is in contact with the semiconductor body layer.

Abstract: The present application discloses an epitaxial growth method for an FDSOI hybrid region, comprising: step 1, providing an FDSOI substrate structure, and forming a hard mask layer; step 2, forming a trench in the entire hybrid region, wherein the bottom surface of the trench is below or level with the top surface of the semiconductor body layer; step 3, performing oxidation to form a first oxide layer on the exposed surfaces of the semiconductor body layer and the semiconductor top layer; step 4, fully etching the first oxide layer, and forming an inner sidewall composed of the remaining first oxide layer on the side surface of the trench in a self-aligned manner; and step 5, performing epitaxial growth to form, in the trench, a semiconductor epitaxial layer in contact with the semiconductor body layer.

Abstract: One aspect of the present disclosure is a method of fabricating metal gate by forming special layers in place of traditional TiN hard mask over the ILD0 layer to avoid ILD0 losses due to conventional ILD0 CMP. The method can comprise: after the ILD0 CMP, forming a first thin ashable film layer over the ILD0 layer; then forming a second thin dielectric layer over the first layer; during the aluminum CMP process for a first region (PMOS or NMOS), removing the second layer through polishing until the top surface of the first ashable film layer; and then removing first ashable film layer through an ashing method such as burning. In this way, ILD0 loss can be reduced during the first aluminum CMP step and thus can reduce initial height of ILD0, which in turn can reduce the height of initial dummy gate filled in the cavity.

Abstract: A novel plasma process is introduced as an improvement over conventional plasma processes during formation of spacers for FinFET devices. Under this novel plasma process, an oxide layer is grown over sidewall materials and low energy plasma gas is used for the over-etching of the corner areas of the sidewalls. The oxide layer can effectively protect the sidewall materials during the over-etching by the low energy plasma gas and thus to reduce the aforementioned CD losses introduced by the low energy plasma gas. This improved low energy plasma etching technique can protect the fin structure from CD losses as compared to the conventional low energy plasma process, and also avoid damaging fin silicon structure with reduced Si losses as compared to the conventional high energy plasma process.

Abstract: One aspect of the present disclosure is a method of fabricating metal gate by forming special layers in place of traditional TiN hard mask over the ILD0 layer to avoid ILD0 losses due to conventional ILD0 CMP. The method can comprise: after the ILD0 CMP, forming a first thin ashable film layer over the ILD0 layer; then forming a second thin dielectric layer over the first layer; during the aluminum CMP process for a first region (PMOS or NMOS), removing the second layer through polishing until the top surface of the first ashable film layer; and then removing first ashable film layer through an ashing method such as burning. In this way, ILD0 loss can be reduced during the first aluminum CMP step and thus can reduce initial height of ILD0, which in turn can reduce the height of initial dummy gate filled in the cavity.

Abstract: A novel plasma process is introduced as an improvement over conventional plasma processes during formation of spacers for FinFET devices. Under this novel plasma process, an oxide layer is grown over sidewall materials and low energy plasma gas is used for the over-etching of the corner areas of the sidewalls. The oxide layer can effectively protect the sidewall materials during the over-etching by the low energy plasma gas and thus to reduce the aforementioned CD losses introduced by the low energy plasma gas. This improved low energy plasma etching technique can protect the fin structure from CD losses as compared to the conventional low energy plasma process, and also avoid damaging fin silicon structure with reduced Si losses as compared to the conventional high energy plasma process.