Patents by Inventor Yoon-Jong Song

Yoon-Jong Song has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190252463
    Abstract: A semiconductor device includes a substrate including a memory cell region and a logic region; a variable resistance memory device on the memory cell region; a logic device on the logic region; a first horizontal bit line extending in a horizontal direction on a surface of the substrate on the memory cell region and electrically connected to the variable resistance memory device; a second horizontal bit line extending in a horizontal direction on the surface of the substrate on the logic region and electrically connected to the logic device; and a vertical bit line electrically connected to the first horizontal bit line and the second horizontal bit line and extending perpendicular to the surface of the substrate.
    Type: Application
    Filed: April 24, 2019
    Publication date: August 15, 2019
    Inventors: Kil-ho Lee, Yoon-jong Song, Gwan-hyeob Koh
  • Patent number: 10319784
    Abstract: A semiconductor device includes a substrate including a memory cell region and a logic region; a variable resistance memory device on the memory cell region; a logic device on the logic region; a first horizontal bit line extending in a horizontal direction on a surface of the substrate on the memory cell region and electrically connected to the variable resistance memory device; a second horizontal bit line extending in a horizontal direction on the surface of the substrate on the logic region and electrically connected to the logic device; and a vertical bit line electrically connected to the first horizontal bit line and the second horizontal bit line and extending perpendicular to the surface of the substrate.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: June 11, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kil-ho Lee, Yoon-jong Song, Gwan-hyeob Koh
  • Patent number: 10163976
    Abstract: A method of manufacturing an MRAM device includes sequentially forming a first insulating interlayer and an etch-stop layer on a substrate. A lower electrode is formed through the etch-stop layer and the first insulating interlayer. An MTJ structure layer and an upper electrode are sequentially formed on the lower electrode and the etch-stop layer. The MTJ structure layer is patterned by a physical etching process using the upper electrode as an etching mask to form an MTJ structure at least partially contacting the lower electrode. The first insulating interlayer is protected by the etch-stop layer so not to be etched by the physical etching process.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: December 25, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ki-Seok Suh, Jae-Chul Shim, Kil-Ho Lee, Yong-Seok Chung, Gwan-Hyeob Koh, Yoon-Jong Song
  • Publication number: 20180350876
    Abstract: A semiconductor device includes a substrate including a memory cell region and a logic region; a variable resistance memory device on the memory cell region; a logic device on the logic region; a first horizontal bit line extending in a horizontal direction on a surface of the substrate on the memory cell region and electrically connected to the variable resistance memory device; a second horizontal bit line extending in a horizontal direction on the surface of the substrate on the logic region and electrically connected to the logic device; and a vertical bit line electrically connected to the first horizontal bit line and the second horizontal bit line and extending perpendicular to the surface of the substrate.
    Type: Application
    Filed: December 29, 2017
    Publication date: December 6, 2018
    Inventors: Kil-ho Lee, Yoon-jong Song, Gwan-hyeob Koh
  • Publication number: 20180351080
    Abstract: In a method of manufacturing an MRAM device, a memory unit including a lower electrode, an MTJ structure and an upper electrode sequentially stacked is formed on a substrate. A protective layer structure including a capping layer, a sacrificial layer and an etch stop layer sequentially stacked is formed on the substrate to cover the memory unit. An insulating interlayer is formed on the protective layer structure. The insulating interlayer is formed to form an opening exposing the protective layer structure. The exposed protective layer structure is partially removed to expose the upper electrode. A wiring is formed on the exposed upper electrode to fill the opening.
    Type: Application
    Filed: July 26, 2018
    Publication date: December 6, 2018
    Inventors: JUNG-HOON BAK, Myoung-Su Son, Jae-Chul Shim, Gwan-Hyeob Koh, Yoon-Jong Song
  • Patent number: 10109676
    Abstract: A magnetic tunnel junction (MTJ) structure includes a fixed layer pattern structure having a perpendicular magnetization direction, a tunnel barrier pattern on the fixed layer pattern structure, a free layer pattern on the tunnel barrier pattern, the free layer pattern having a perpendicular magnetization direction, a first surface magnetism induction pattern on the free layer pattern, the first surface magnetism induction pattern inducing a perpendicular magnetism in a surface of the free layer pattern, a conductive pattern on the first surface magnetism induction pattern, and a ferromagnetic pattern on the conductive pattern.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: October 23, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Hoon Bak, Woo-Jin Kim, Mina Lee, Gwan-Hyeob Koh, Yoon-Jong Song
  • Patent number: 10056543
    Abstract: In a method of manufacturing an MRAM device, a memory unit including a lower electrode, an MTJ structure and an upper electrode sequentially stacked is formed on a substrate. A protective layer structure including a capping layer, a sacrificial layer and an etch stop layer sequentially stacked is formed on the substrate to cover the memory unit. An insulating interlayer is formed on the protective layer structure. The insulating interlayer is formed to form an opening exposing the protective layer structure. The exposed protective layer structure is partially removed to expose the upper electrode. A wiring is formed on the exposed upper electrode to fill the opening.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: August 21, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Hoon Bak, Myoung-Su Son, Jae-Chul Shim, Gwan-Hyeob Koh, Yoon-Jong Song
  • Publication number: 20180012933
    Abstract: A method of manufacturing an MRAM device includes sequentially forming a first insulating interlayer and an etch-stop layer on a substrate. A lower electrode is formed through the etch-stop layer and the first insulating interlayer. An MTJ structure layer and an upper electrode are sequentially formed on the lower electrode and the etch-stop layer. The MTJ structure layer is patterned by a physical etching process using the upper electrode as an etching mask to form an MTJ structure at least partially contacting the lower electrode. The first insulating interlayer is protected by the etch-stop layer so not to be etched by the physical etching process.
    Type: Application
    Filed: September 21, 2017
    Publication date: January 11, 2018
    Inventors: Ki-Seok SUH, Jae-Chul SHIM, Kil-Ho LEE, Yong-Seok CHUNG, Gwan-Hyeob KOH, Yoon-Jong SONG
  • Patent number: 9853087
    Abstract: A method of manufacturing an MRAM device includes sequentially forming a first insulating interlayer and an etch-stop layer on a substrate. A lower electrode is formed through the etch-stop layer and the first insulating interlayer. An MTJ structure layer and an upper electrode are sequentially formed on the lower electrode and the etch-stop layer. The MTJ structure layer is patterned by a physical etching process using the upper electrode as an etching mask to form an MTJ structure at least partially contacting the lower electrode. The first insulating interlayer is protected by the etch-stop layer so not to be etched by the physical etching process.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: December 26, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ki-Seok Suh, Jae-Chul Shim, Kil-Ho Lee, Yong-Seok Chung, Gwan-Hyeob Koh, Yoon-Jong Song
  • Publication number: 20170110509
    Abstract: A magnetic tunnel junction (MTJ) structure includes a fixed layer pattern structure having a perpendicular magnetization direction, a tunnel barrier pattern on the fixed layer pattern structure, a free layer pattern on the tunnel barrier pattern, the free layer pattern having a perpendicular magnetization direction, a first surface magnetism induction pattern on the free layer pattern, the first surface magnetism induction pattern inducing a perpendicular magnetism in a surface of the free layer pattern, a conductive pattern on the first surface magnetism induction pattern, and a ferromagnetic pattern on the conductive pattern.
    Type: Application
    Filed: October 14, 2016
    Publication date: April 20, 2017
    Inventors: Jung-Hoon BAK, Woo-Jin KIM, Mina LEE, Gwan-Hyeob KOH, Yoon-Jong SONG
  • Publication number: 20170069684
    Abstract: A method of manufacturing an MRAM device includes sequentially forming a first insulating interlayer and an etch-stop layer on a substrate. A lower electrode is formed through the etch-stop layer and the first insulating interlayer. An MTJ structure layer and an upper electrode are sequentially formed on the lower electrode and the etch-stop layer. The MTJ structure layer is patterned by a physical etching process using the upper electrode as an etching mask to form an MTJ structure at least partially contacting the lower electrode. The first insulating interlayer is protected by the etch-stop layer so not to be etched by the physical etching process.
    Type: Application
    Filed: May 17, 2016
    Publication date: March 9, 2017
    Inventors: Ki-Seok SUH, Jae-Chul SHIM, Kil-Ho LEE, Yong-Seok CHUNG, Gwan-Hyeob KOH, Yoon-Jong SONG
  • Publication number: 20170054070
    Abstract: In a method of manufacturing an MRAM device, a memory unit including a lower electrode, an MTJ structure and an upper electrode sequentially stacked is formed on a substrate. A protective layer structure including a capping layer, a sacrificial layer and an etch stop layer sequentially stacked is formed on the substrate to cover the memory unit. An insulating interlayer is formed on the protective layer structure. The insulating interlayer is formed to form an opening exposing the protective layer structure. The exposed protective layer structure is partially removed to expose the upper electrode. A wiring is formed on the exposed upper electrode to fill the opening.
    Type: Application
    Filed: May 4, 2016
    Publication date: February 23, 2017
    Inventors: Jung-Hoon Bak, Myoung-Su Son, Jae-Chul Shim, Gwan-Hyeob Koh, Yoon-Jong Song
  • Patent number: 9484526
    Abstract: Provided are a magnetic memory device and a method of forming the same. The magnetic memory device includes a magnetic tunnel junction pattern located on a substrate and including magnetic patterns and a tunnel barrier pattern located between the magnetic patterns, and a first crystallinity conserving pattern located on the magnetic tunnel junction pattern and having a higher crystallization temperature than the magnetic patterns. The first crystallinity conserving pattern is amorphous.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: November 1, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dae-Eun Jeong, Sang-Yong Kim, Yoon-Jong Song
  • Patent number: 9431610
    Abstract: A phase change memory device includes a phase change memory unit and a heat sink. The phase change memory unit includes a phase change material layer pattern, a lower electrode beneath the phase change material layer pattern configured to heat the phase change material layer pattern, and an upper electrode on the phase change material layer pattern. The heat sink configured to absorb heat from the phase change memory unit. The heat sink has a top surface lower than a top surface of the upper electrode and is spaced apart from the phase change memory unit.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: August 30, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae-Jin Park, Yoon-Jong Song, Chil-Hee Chung
  • Publication number: 20160020393
    Abstract: A phase change memory device includes a phase change memory unit and a heat sink. The phase change memory unit includes a phase change material layer pattern, a lower electrode beneath the phase change material layer pattern configured to heat the phase change material layer pattern, and an upper electrode on the phase change material layer pattern. The heat sink configured to absorb heat from the phase change memory unit. The heat sink has a top surface lower than a top surface of the upper electrode and is spaced apart from the phase change memory unit.
    Type: Application
    Filed: September 28, 2015
    Publication date: January 21, 2016
    Inventors: Tae-Jin PARK, Yoon-Jong SONG, Chil-Hee CHUNG
  • Publication number: 20160020384
    Abstract: Provided are a magnetic memory device and a method of forming the same. The magnetic memory device includes a magnetic tunnel junction pattern located on a substrate and including magnetic patterns and a tunnel barrier pattern located between the magnetic patterns, and a first crystallinity conserving pattern located on the magnetic tunnel junction pattern and having a higher crystallization temperature than the magnetic patterns. The first crystallinity conserving pattern is amorphous.
    Type: Application
    Filed: March 12, 2015
    Publication date: January 21, 2016
    Inventors: Dae-Eun JEONG, Sang-Yong KIM, Yoon-Jong SONG
  • Publication number: 20130320290
    Abstract: A phase change memory device includes a phase change memory unit and a heat sink. The phase change memory unit includes a phase change material layer pattern, a lower electrode beneath the phase change material layer pattern configured to heat the phase change material layer pattern, and an upper electrode on the phase change material layer pattern. The heat sink configured to absorb heat from the phase change memory unit. The heat sink has a top surface lower than a top surface of the upper electrode and is spaced apart from the phase change memory unit.
    Type: Application
    Filed: January 24, 2013
    Publication date: December 5, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae-Jin PARK, Yoon-Jong SONG, Chil-Hee CHUNG
  • Publication number: 20120175580
    Abstract: A method of fabricating a phase change memory includes forming a lower electrode on a semiconductor substrate, forming a phase change pattern, an upper electrode, and a hard mask pattern sequentially on the lower electrode, a width of a bottom surface of the hard mask pattern being greater than a width of a top surface of the hard mask pattern, the bottom surface of the hard mask pattern facing the upper electrode and being opposite the top surface of the hard mask pattern, and forming a capping layer to cover the top surface of the hard mask pattern and sidewalls of the hard mask pattern, phase change pattern, and upper electrode.
    Type: Application
    Filed: March 26, 2012
    Publication date: July 12, 2012
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Yoon-Jong SONG, Byung-Seo Kim, Kyung-Chang Ryoo
  • Patent number: 8203135
    Abstract: A semiconductor device, a semiconductor module, an electronic apparatus and methods of fabricating and manufacturing the same are provided. The semiconductor device includes a lower interconnection formed on a substrate, a plurality of control patterns formed on the lower interconnection, a plurality of lower contact plug patterns formed on the control patterns, a plurality of storage patterns formed on the lower contact plug patterns, a plurality of upper electrodes formed on the storage patterns, and a plurality of upper interconnections formed on the upper electrodes. The lower contact plug patterns each include at least two contact holes having different sizes, a plurality of sidewall patterns formed on inner sidewalls of the two contact holes and wherein the sidewall patterns have different thicknesses from one another.
    Type: Grant
    Filed: February 1, 2010
    Date of Patent: June 19, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyu-Rie Sim, Jung-Hoon Park, Yoon-Jong Song, Jae-Min Shin, Shin-Hee Han
  • Patent number: 8164079
    Abstract: A method of fabricating a phase change memory includes forming a lower electrode on a semiconductor substrate, forming a phase change pattern, an upper electrode, and a hard mask pattern sequentially on the lower electrode, a width of a bottom surface of the hard mask pattern being greater than a width of a top surface of the hard mask pattern, the bottom surface of the hard mask pattern facing the upper electrode and being opposite the top surface of the hard mask pattern, and forming a capping layer to cover the top surface of the hard mask pattern and sidewalls of the hard mask pattern, phase change pattern, and upper electrode.
    Type: Grant
    Filed: April 22, 2011
    Date of Patent: April 24, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yoon-Jong Song, Byung-Seo Kim, Kyung-Chang Ryoo