Patents by Inventor Yoshiaki Asao

Yoshiaki Asao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190288193
    Abstract: According to one embodiment, a nonvolatile memory device includes a first conductive portion, an insulating film surrounding a side surface of the first conductive portion, an intermediate layer provided on the first conductive portion and the insulating film, a first film including a first portion provided on the intermediate layer and at least one second portion provided in the intermediate layer and outside an upper edge of the first conductive portion, the first film including, above the first conductive portion, a resistance change portion that has a first resistance state and a second resistance state having resistance higher than resistance in the first resistance state, and a second conductive portion provided at least on the resistance change portion.
    Type: Application
    Filed: August 31, 2018
    Publication date: September 19, 2019
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshiaki ASAO, Misako MOROTA, Yoshiki KAMATA, Yukihiro NOMURA, Iwao KUNISHIMA
  • Patent number: 10153429
    Abstract: A memory device according to an embodiment includes a first conductive layer, a second conductive layer, a third conductive layer intersecting the first conductive layer and the second conductive layer, and a resistance change layer including a first region which is provided between the first conductive layer and the third conductive layer and has a superlattice structure, a second region which is provided between the second conductive layer and the third conductive layer and has the superlattice structure, and a third region which is provided between the first region and the second region. The third region includes at least one element selected from the group consisting of O, F, C, P, B, N, H, Bi, Cd, Zn, Ga, Se, Al, S, Be, In, and Pb. Concentration of the at least one element in the third region is higher than that in the first region and the second region.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: December 11, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Yoshiki Kamata, Yoshiaki Asao, Iwao Kunishima, Misako Morota
  • Publication number: 20180254412
    Abstract: According to one embodiment, a semiconductor includes a first wiring, a second wiring, a first electrode, a second electrode and a memory cell. The first wiring extends in a first direction. The second wiring extends in a second direction crossing the first direction. The first electrode is connected to the first wiring. The second electrode is connected to the second wiring. The memory cell is arranged between the first electrode and the second electrode. The memory cell includes a memory element electrically connected to the first electrode, and a selector provided between the memory element and the second electrode and electrically connected to the second electrode, and the memory element and the selector are of a same conductivity type.
    Type: Application
    Filed: February 28, 2018
    Publication date: September 6, 2018
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Yoshiaki ASAO
  • Publication number: 20180006216
    Abstract: A memory device according to an embodiment includes a first conductive layer, a second conductive layer, a third conductive layer intersecting the first conductive layer and the second conductive layer, and a resistance change layer including a first region which is provided between the first conductive layer and the third conductive layer and has a superlattice structure, a second region which is provided between the second conductive layer and the third conductive layer and has the superlattice structure, and a third region which is provided between the first region and the second region. The third region includes at least one element selected from the group consisting of O, F, C, P, B, N, H, Bi, Cd, Zn, Ga, Se, Al, S, Be, In, and Pb. Concentration of the at least one element in the third region is higher than that in the first region and the second region.
    Type: Application
    Filed: June 28, 2017
    Publication date: January 4, 2018
    Inventors: Yoshiki KAMATA, Yoshiaki ASAO, Iwao KUNISHIMA, Misako MOROTA
  • Patent number: 9830968
    Abstract: A magnetic memory according to an embodiment includes: at least one memory cell, the memory cell comprising: a conductive layer including a first terminal, a second terminal, and a portion located between the first terminal and the second terminal; a magnetoresistive element including: a first magnetic layer; a second magnetic layer between the portion and the first magnetic layer; and a nonmagnetic layer between the first magnetic layer and the second magnetic layer; a diode including an anode and a cathode, one of the anode and the cathode being electrically connected to the first magnetic layer; and a transistor including third and fourth terminals and a control terminal, the third terminal being electrically connected to the first terminal.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: November 28, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Naoharu Shimomura, Yoshiaki Asao, Takamitsu Ishihara
  • Patent number: 9812639
    Abstract: According to an embodiment, a non-volatile memory device includes a first interconnection, a second interconnection closest to the first interconnection in a first direction, rectifying portions arranged in the first direction between the first interconnection and the second interconnection, and a first resistance change portion arranged between adjacent ones of the rectifying portions in the first direction. Each of the rectifying portions includes a first metal oxide layer and a second metal oxide layer.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: November 7, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Koji Matsuo, Yoshiaki Asao, Kunifumi Suzuki
  • Publication number: 20170270985
    Abstract: A magnetic memory according to an embodiment includes: at least one memory cell, the memory cell comprising: a conductive layer including a first terminal, a second terminal, and a portion located between the first terminal and the second terminal; a magnetoresistive element including: a first magnetic layer; a second magnetic layer between the portion and the first magnetic layer; and a nonmagnetic layer between the first magnetic layer and the second magnetic layer; a diode including an anode and a cathode, one of the anode and the cathode being electrically connected to the first magnetic layer; and a transistor including third and fourth terminals and a control terminal, the third terminal being electrically connected to the first terminal.
    Type: Application
    Filed: September 15, 2016
    Publication date: September 21, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Naoharu SHIMOMURA, Yoshiaki ASAO, Takamitsu ISHIHARA
  • Patent number: 9385160
    Abstract: A memory includes a semiconductor substrate. Magnetic tunnel junction elements are provided above the semiconductor substrate. Each of the magnetic tunnel junction elements stores data by a change in a resistance state, and the data is rewritable by a current. Cell transistors are provided on the semiconductor substrate. Each of the cell transistors is in a conductive state when the current is applied to the corresponding magnetic tunnel junction element. Gate electrodes are included in the respective cell transistors. Each of the gate electrodes controls the conductive state of the corresponding cell transistor. In active areas, the cell transistors are provided, and the active areas extend in an extending direction of intersecting the gate electrodes at an angle of (90?atan(?)) degrees.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: July 5, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Yoshiaki Asao
  • Patent number: 9384829
    Abstract: A memory device includes n (n being an integer of 2 or more) resistance change films being series connected to each other. Each of the resistance change films is a superlattice film in which plural pairs of a first crystal layer made of a first compound and a second crystal layer made of a second compound are alternately stacked. An average composition of the entire resistance change film or an arrangement pitch of the first crystal layers and the second crystal layers are mutually different among the n resistance change films.
    Type: Grant
    Filed: March 20, 2013
    Date of Patent: July 5, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hironobu Furuhashi, Iwao Kunishima, Susumu Shuto, Yoshiaki Asao, Gaku Sudo
  • Patent number: 9368553
    Abstract: According to one embodiment, a memory device includes a first active area, formed on the substrate, which extends in a third direction. The memory device also includes three gate electrodes, provided on the first active area, which extend in a second direction intersecting the third direction. The memory device also includes at least two or more upper-layer interconnects and at least two or more lower-layer interconnects, provided on the first active area, which extend in a first direction intersecting the second direction and the third direction. The memory device also includes first transistors of three, each of them is provided at the intersection point between the first active area and the three gate electrodes. The memory device also includes the first transistors of three are one device isolation transistor and two cell transistors.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: June 14, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshiaki Asao
  • Publication number: 20160099290
    Abstract: According to one embodiment, a memory device includes a first gate electrode, a second gate electrode, a third gate electrode, a first active area and a second active area on a substrate. The first to the third gate electrodes extend in a first direction. The first active area and the second active area extend in a second direction. The first direction and the second direction cross each other. The memory device includes a first contact, a second contact, a third contact, a fourth contact, variable resistance layer, a first interconnection layer, a second interconnection layer and the second interconnection layer. The variable resistance layer and the first interconnection layer extend in the first direction. The second interconnection layer and the third interconnection layer extend in the second direction.
    Type: Application
    Filed: March 4, 2015
    Publication date: April 7, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Yoshiaki ASAO
  • Publication number: 20160093674
    Abstract: According to one embodiment, a memory device includes a first active area, formed on the substrate, which extends in a third direction. The memory device also includes three gate electrodes, provided on the first active area, which extend in a second direction intersecting the third direction. The memory device also includes at least two or more upper-layer interconnects and at least two or more lower-layer interconnects, provided on the first active area, which extend in a first direction intersecting the second direction and the third direction. The memory device also includes first transistors of three, each of them is provided at the intersection point between the first active area and the three gate electrodes. The memory device also includes the first transistors of three are one device isolation transistor and two cell transistors.
    Type: Application
    Filed: February 18, 2015
    Publication date: March 31, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Yoshiaki ASAO
  • Publication number: 20160071906
    Abstract: A memory includes a semiconductor substrate. Magnetic tunnel junction elements are provided above the semiconductor substrate. Each of the magnetic tunnel junction elements stores data by a change in a resistance state, and the data is rewritable by a current. Cell transistors are provided on the semiconductor substrate. Each of the cell transistors is in a conductive state when the current is applied to the corresponding magnetic tunnel junction element. Gate electrodes are included in the respective cell transistors. Each of the gate electrodes controls the conductive state of the corresponding cell transistor. In active areas, the cell transistors are provided, and the active areas extend in an extending direction of intersecting the gate electrodes at an angle of (90?atan(?)) degrees.
    Type: Application
    Filed: November 18, 2015
    Publication date: March 10, 2016
    Inventor: Yoshiaki ASAO
  • Patent number: 9263501
    Abstract: According to one embodiment, a memory device includes a first diffusion layer region on, a second diffusion layer region, a third diffusion layer region, a first gate electrode and a second gate electrode. The memory device also includes a first via contact group, a second via contact group and a variable resistance element. At least one of the plurality of first via contacts is electrically connected to the first diffusion layer region with one end and at least one of the plurality of second via contacts is electrically connected to the third diffusion layer region with one end. The variable resistance element being electrically a first interconnect layer.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: February 16, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshiaki Asao
  • Patent number: 9263666
    Abstract: A magnetic random access memory which is a memory cell array including a magnetoresistive effect element having a fixed layer whose magnetization direction is fixed, a recording layer whose magnetization direction is reversible, and a non-magnetic layer provided between the fixed layer and the recording layer, wherein all conductive layers in the memory cell array arranged below the magnetoresistive effect element are formed of materials each containing an element selected from a group including W, Mo, Ta, Ti, Zr, Nb, Cr, Hf, V, Co, and Ni.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: February 16, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takeshi Kajiyama, Yoshiaki Asao
  • Patent number: 9224786
    Abstract: A memory includes a semiconductor substrate. Magnetic tunnel junction elements are provided above the semiconductor substrate. Each of the magnetic tunnel junction elements stores data by a change in a resistance state, and the data is rewritable by a current. Cell transistors are provided on the semiconductor substrate. Each of the cell transistors is in a conductive state when the current is applied to the corresponding magnetic tunnel junction element. Gate electrodes are included in the respective cell transistors. Each of the gate electrodes controls the conductive state of the corresponding cell transistor. In active areas, the cell transistors are provided, and the active areas extend in an extending direction of intersecting the gate electrodes at an angle of (90?a tan(1/3)) degrees.
    Type: Grant
    Filed: May 20, 2015
    Date of Patent: December 29, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Yoshiaki Asao
  • Patent number: 9190453
    Abstract: According to one embodiment, a magnetic memory including an isolation region with an insulator in a trench is disclosed. The isolation region defines active areas extending in a 1st direction and having 1st and 2nd active areas, an isolation region extending in a 2nd direction perpendicular to the 1st direction exists between the 1st and 2nd active areas. 1st and 2nd word lines extending in the 2nd direction are buried in a surface of semiconductor substrate. 1st and 2nd select transistors connected to the word lines are on the 1st active area. 1st and 2nd variable resistance elements connected to drain regions of the 1st and 2nd select transistors are on the 1st active area.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: November 17, 2015
    Inventors: Takashi Nakazawa, Yoshiaki Asao, Takeshi Kajiyama, Kenji Noma
  • Patent number: 9165628
    Abstract: A semiconductor memory device includes: a plurality of word lines extending in a first direction; first to third bit lines extending in a second direction that intersects with the first direction; a plurality of variable resistance elements each having a first terminal connected to either one of the first and third bit lines; a plurality of active areas extending in a direction oblique to the first direction while intersecting with the first to third bit lines; a plurality of select transistors provided on the active areas and each having a gate connected to a corresponding one of the word lines, and a current path whose one end is connected to a second terminal of a corresponding one of the variable resistance elements; and a plurality of contact plugs each connecting the other end of the current path of a corresponding one of the select transistors to the second bit line, wherein each of the active areas includes two select transistors sharing a diffusion region, the variable resistance elements includes a
    Type: Grant
    Filed: June 9, 2015
    Date of Patent: October 20, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Toshiharu Watanabe, Yoshiaki Asao
  • Publication number: 20150269983
    Abstract: A semiconductor memory device includes: a plurality of word lines extending in a first direction; first to third bit lines extending in a second direction that intersects with the first direction; a plurality of variable resistance elements each having a first terminal connected to either one of the first and third bit lines; a plurality of active areas extending in a direction oblique to the first direction while intersecting with the first to third bit lines; a plurality of select transistors provided on the active areas and each having a gate connected to a corresponding one of the word lines, and a current path whose one end is connected to a second terminal of a corresponding one of the variable resistance elements; and a plurality of contact plugs each connecting the other end of the current path of a corresponding one of the select transistors to the second bit line, wherein each of the active areas includes two select transistors sharing a diffusion region, the variable resistance elements includes a
    Type: Application
    Filed: June 9, 2015
    Publication date: September 24, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Toshiharu WATANABE, Yoshiaki Asao
  • Publication number: 20150255506
    Abstract: A memory includes a semiconductor substrate. Magnetic tunnel junction elements are provided above the semiconductor substrate. Each of the magnetic tunnel junction elements stores data by a change in a resistance state, and the data is rewritable by a current. Cell transistors are provided on the semiconductor substrate. Each of the cell transistors is in a conductive state when the current is applied to the corresponding magnetic tunnel junction element. Gate electrodes are included in the respective cell transistors. Each of the gate electrodes controls the conductive state of the corresponding cell transistor. In active areas, the cell transistors are provided, and the active areas extend in an extending direction of intersecting the gate electrodes at an angle of (90?a tan(1/3)) degrees.
    Type: Application
    Filed: May 20, 2015
    Publication date: September 10, 2015
    Inventor: Yoshiaki ASAO