Patents by Inventor Yoshiaki Takemura

Yoshiaki Takemura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6781202
    Abstract: A higher-performance short channel MOS transistor with enhanced resistance to soft errors caused by exposure to high-energy rays is realized. At the time of forming a deep source/drain diffusion layer region at high density, an intermediate region of a density higher than that of impurity of a semiconductor substrate is formed between the source/drain diffusion layer and the semiconductor substrate of a conduction type opposite to that of the source/drain diffusion layer. The intermediate region is formed with a diffusion window for forming the source/drain, an intermediate layer of uniform concentration and uniform width can be realized at low cost.
    Type: Grant
    Filed: November 26, 2002
    Date of Patent: August 24, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Ken Yamaguchi, Yoshiaki Takemura, Kenichi Osada, Masatada Horiuchi, Takashi Uchino
  • Publication number: 20030137012
    Abstract: A higher-performance short channel MOS transistor with enhanced resistance to soft errors caused by exposure to high-energy rays is realized. At the time of forming a deep source/drain diffusion layer region at high density, an intermediate region of a density higher than that of impurity of a semiconductor substrate is formed between the source/drain diffusion layer and the semiconductor substrate of a conduction type opposite to that of the source/drain diffusion layer. The intermediate region is formed with a diffusion window for forming the source/drain, an intermediate layer of uniform concentration and uniform width can be realized at low cost.
    Type: Application
    Filed: November 26, 2002
    Publication date: July 24, 2003
    Inventors: Ken Yamaguchi, Yoshiaki Takemura, Kenichi Osada, Masatada Horiuchi, Takashi Uchino
  • Patent number: 5233205
    Abstract: A novel concept and structure of a semiconductor circuit are disclosed which utilize the fact that the interaction between the carriers such as electrons and holes supplied in a meso-scopic region and the potential field formed in the meso-scopic region leads to such effects as quantum interference and resonance, with the result that the output intensity is changed.
    Type: Grant
    Filed: June 22, 1992
    Date of Patent: August 3, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Toshiyuki Usagawa, Shirun Ho, Ken Yamaguchi, Yoshiaki Takemura
  • Patent number: 5042027
    Abstract: A communication network system includes a communication line, a plurality of communication stations each having a node coupled to the communication line and a network controller coupled to the stations for controlling routing for communication messages between nodes. In one embodiment, the messages are sent from plural terminals connected with each node along with communication performance prerequisites. The communication performance prerequisites for a communication message are discriminated in the node which receives the message. Traffic in various routes between the nodes is continually measured in the communication stations and the measuring results are stored in a database storage unit.
    Type: Grant
    Filed: September 8, 1989
    Date of Patent: August 20, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Akihiko Takase, Masahiro Takatori, Yoshiaki Takemura, Naoya Kobayashi, Yasushi Sawada, Yukio Nakano, Yasushi Takahashi, Masahiro Koya, Yoshitaka Takasaki