Abstract: An optical waveguide is provided with a substrate 1, a lower cladding layer 2 that is formed on the substrate 1, an optical signal transmitting core pattern 31 and a protruding pattern 32 that are disposed on the lower cladding layer 2, and an upper cladding layer 4 that is disposed in a manner that it covers the optical signal transmitting core pattern 31 in association with the lower cladding layer 2. The protruding pattern 32 has an outer peripheral wall 33 that protrudes out of the substrate 1, the lower cladding layer 2, and the upper cladding layer 4 in an outer peripheral direction of the substrate 1.

Abstract: It is an object of the invention to provide a method for producing a substrate for mounting a semiconductor chip, that can reduce bridging and allows excellent wire bondability and solder connection reliability to be obtained, even when forming fine-pitch wirings.

Abstract: It is an object of the invention to provide a method for producing a substrate for mounting a semiconductor chip, that can reduce bridging and allows excellent wire bondability and solder connection reliability to be obtained, even when forming fine-pitch wirings.

Abstract: A semiconductor package substrate is provided, which can meet the move toward high integration of semiconductors. A nickel layer is plated on an electroplated copper foil to form a wiring pattern. An LSI chip is mounted on the copper foil, and terminals of the LSI chip and the wiring pattern are connected by wire bonding, followed by sealing with a semiconductor-sealing epoxy resin. Only the copper foil is dissolved away with an alkali etchant to expose nickel. With a nickel stripper having low copper-dissolving power, the nickel layer is removed to expose the wiring pattern. A solder resist is coated, and a pattern is formed in such a way that connecting terminal portions are exposed. Solder balls are placed at the exposed portions of the wiring pattern and are then fused. The wiring pattern is connected to an external printed board via the solder balls.

Abstract: A semiconductor package substrate is provided, which can meet the move toward high integration of semiconductors. A nickel layer is plated on an electroplated copper foil to form a wiring pattern. An LSI chip is mounted on the copper foil, and terminals of the LSI chip and the wiring pattern are connected by wire bonding, followed by sealing with a semiconductor-sealing epoxy resin. Only the copper foil is dissolved away with an alkali etchant to expose nickel. With a nickel stripper having low copper-dissolving power, the nickel layer is removed to expose the wiring pattern. A solder resist is coated, and a pattern is formed in such a way that connecting terminal portions are exposed. Solder balls are placed at the exposed portions of the wiring pattern and are then fused. The wiring pattern is connected to an external printed board via the solder balls.

Abstract: A semiconductor package substrate is provided, which can meet the move toward high integration of semiconductors. A nickel layer is plated on an electroplated copper foil to form a wiring pattern. An LSI chip is mounted on the copper foil, and terminals of the LSI chip and the wiring pattern are connected by wire bonding, followed by sealing with a semiconductor-sealing epoxy resin. Only the copper foil is dissolved away with an alkali etchant to expose nickel. With a nickel stripper having low copper-dissolving power, the nickel layer is removed to expose the wiring pattern. A solder resist is coated, and a pattern is formed in such a way that connecting terminal portions are exposed. Solder balls are placed at the exposed portions of the wiring pattern and are then fused. The wiring pattern is connected to an external printed board via the solder balls.

Abstract: The present invention provides a process for the fabrication of a wiring board, which comprises the following steps: (a) forming a first wiring pattern on a first side of a self-supporting carrier metal foil so as to obtain a self-supporting wiring sheet comprising the carrier metal foil and the first wiring pattern; (b) superposing and pressing the first side of said self-supporting wiring sheet on and against an insulating substrate so that the first wiring pattern is_embedded in the insulating substrate and constitutes a surface with the insulating substrate; and (c) etching off desired portions of said carrier metal foil to form a second wiring pattern made of said carrier metal foil remaining on the surface constituted by the insulating substrate and the first wiring pattern. The present invention also provides the wiring board for electrical tests so fabricated.

Abstract: A semiconductor package substrate is provided, which can meet the move toward high integration of semiconductors. A nickel layer is plated on an electroplated copper foil to form a wiring pattern. An LSI chip is mounted on the copper foil, and terminals of the LSI chip and the wiring pattern are connected by wire bonding, followed by sealing with a semiconductor-sealing epoxy resin. Only the copper foil is dissolved away with an alkali etchant to expose nickel. With a nickel stripper having low copper-dissolving power, the nickel layer is removed to expose the wiring pattern. A solder resist is coated, and a pattern is formed in such a way that connecting terminal portions are exposed. Solder balls are placed at the exposed portions of the wiring pattern and are then fused. The wiring pattern is connected to an external printed board via the solder balls.

Abstract: A semiconductor package substrate is provided, which can meet the move toward high integration of semiconductors. A nickel layer is plated on an electroplated copper foil to form a wiring pattern. An LSI chip is mounted on the copper foil, and terminals of the LSI chip and the wiring pattern are connected by wire bonding, followed by sealing with a semiconductor-sealing epoxy resin. Only the copper foil is dissolved away with an alkali etchant to expose nickel. With a nickel stripper having low copper-dissolving power, the nickel layer is removed to expose the wiring pattern. A solder resist is coated, and a pattern is formed in such a way that connecting terminal portions are exposed. Solder balls are placed at the exposed portions of the wiring pattern and are then fused. The wiring pattern is connected to an external printed board via the solder balls.

Abstract: A semiconductor package substrate is provided, which can meet the move toward high integration of semiconductors. A nickel layer is plated on an electroplated copper foil to form a wiring pattern. An LSI chip is mounted on the copper foil, and terminals of the LSI chip and the wiring pattern are connected by wire bonding, followed by sealing with a semiconductor-sealing epoxy resin. Only the copper foil is dissolved away with an alkali etchant to expose nickel. With a nickel stripper having low copper-dissolving power, the nickel layer is removed to expose the wiring pattern. A solder resist is coated, and a pattern is formed in such a way that connecting terminal portions are exposed. Solder balls are placed at the exposed portions of the wiring pattern and are then fused. The wiring pattern is connected to an external printed board via the solder balls.

Abstract: A semiconductor packaging chip-supporting substrate of the present invention comprises an insulating supporting substrate, wiring provided on the substrate, and an insulating film provided on the wiring. The wiring each have i) an inner connection that connects to a semiconductor chip electrode and ii) a semiconductor chip-mounting region. An opening is also provided in the insulating supporting substrate at its part where each of the wiring is formed on the insulating supporting substrate, which is the part where an outer connection conducting to the inner connection is provided. The insulating film is formed at the part on which the semiconductor chip is mounted, covering the semiconductor chip-mounting region of the wiring.

Abstract: To provide a highly reliable semiconductor device structure that enables cost reduction in the production of packages, inclusive of the cost for chips, and may cause less changes in connection resistance even under conditions of a long-term environmental resistance test. In a semiconductor device comprising a semiconductor chip face-down bonded to a wiring board, it has a structure wherein projecting metal portions are provided at the opposing wiring board terminals without forming bumps on bonding pads of the chip, the whole chip surface is bonded with an organic, anisotropic conductive adhesive material, and the whole or at least an edge of the back of the chip is covered with a sealing material.

Abstract: A wiring board for electrical tests; having an insulating substrate, wiring of predetermined pattern which is embedded in the insulating substrate, and bump electrodes which are formed on the wiring and which are respectively brought into contact with corresponding electrodes of an article to-be-tested. Thus, even when the electrode pitch of the article to-be-tested such as a semiconductor device has become smaller(for example, less than 0.1 [mm]), the electrodes can be formed so as to cope with the electrical tests of the article.

Abstract: A semiconductor packaging chip-supporting substrate of the present invention comprises an insulating supporting substrate, wiring provided on the substrate, and an insulating film provided on the wiring. The wiring each have i) an inner connection that connects to a semiconductor chip electrode and ii) a semiconductor chip-mounting region. An opening is also provided in the insulating supporting a substrate at its part where each of the wiring is formed on the insulating supporting substrate, which is the part where an outer connection conducting to the inner connection is provided. The insulating film is formed at the part on which the semiconductor chip is mounted, covering the semiconductor chip-mounting region of the wiring.

Abstract: A semiconductor package substrate is provided, which can meet the move toward high integration of semiconductors. A nickel layer is plated on an electroplated copper foil to form a wiring pattern. An LSI chip is mounted on the copper foil, and terminals of the LSI chip and the wiring pattern are connected by wire bonding, followed by sealing with a semiconductor-sealing epoxy resin. Only the copper foil is dissolved away with an alkali etchant to expose nickel. With a nickel stripper having low copper-dissolving power, the nickel layer is removed to expose the wiring pattern. A solder resist is coated, and a pattern is formed in such a way that connecting terminal portions are exposed. Solder balls are placed at the exposed portions of the wiring pattern and are then fused. The wiring pattern is connected to an external printed board via the solder balls.

Abstract: A wiring board is fabricated through the following steps:(A) forming, on one side of an elongated carrier metal foil made of a first metal, a thin layer with a second metal whose etching conditions are different from those of the first metal;(B) forming, on a surface of the thin layer, a desired wiring pattern with a third metal whose etching conditions are different from those of the second metal;(C) superposing the carrier metal foil on an insulating substrate with the side of the wiring pattern being positioned inside, whereby the wiring pattern is embedded in the insulating substrate; and(D) etching off the carrier metal foil and the thin layer at desired parts thereof.

Abstract: The object of the present invention is to provide a wiring board fabrication process which is, not only so smooth on the surface that a fine wiring pattern can be formed thereon, but also suitable for mounting electronic parts having fine pitch terminals.The present invention is a fabrication process of a wiring board which comprises a wiring conductive line embedded in the surface of an insulating substrate so that the upper face of the conductive line and the surface of the substrate are flat, and a through-hole land which is a conductive portion projected from the surface of the substrate in a through-hole portion, which is characterized in removing the conductive portion projected from the surface of the substrate in the through-hole portion so as to have a flat surface on the surface of the substrate.

Abstract: A wiring board is fabricated through the following steps:(A) forming, on one side of an elongated carrier metal foil made of a first metal, a thin layer with a second metal whose etching conditions are different from those of the first metal;(B) forming, on a surface of the thin layer, a desired wiring pattern with a third metal whose etching conditions are different from those of the second metal;(C) superposing the carrier metal foil on an insulating substrate with the side of the wiring pattern being positioned inside, whereby the wiring pattern is embedded in the insulating substrate; and(D) etching off the carrier metal foil and the thin layer at desired parts thereof.

Abstract: A wiring board comprising (A) a base substrate on which the necessary wiring pattern has already been formed, and (B) a multi-layer substrate bonded to the wiring pattern side of said base substrate (A) and comprising heat-resistant resin layers and thin-film wiring patterns formed by a thin film forming method under vacuum can mount LSI chips on the substrate and realize increased density of signal wiring.