Patents by Inventor Yoshiaki Ueda

Yoshiaki Ueda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240105917
    Abstract: According to one embodiment, provided is an active material including a niobium titanium-containing oxide phase and a carbon coating layer. The niobium titanium-containing oxide phase contains a niobium titanium-containing oxide having a monoclinic structure and Na, and a Na content therein is 0 ppm or more and 100 ppm or less. The carbon coating layer coats at least a part of the niobium titanium-containing oxide phase, and contains 0.001% or more of carboxyl group.
    Type: Application
    Filed: February 27, 2023
    Publication date: March 28, 2024
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yasuhiro HARADA, Taro FUKAYA, Yasunobu YAMASHITA, Kakuya UEDA, Yoshiaki MURATA, Norio TAKAMI
  • Publication number: 20240088385
    Abstract: In general, according to one embodiment, a niobium-titanium oxide is provided. The niobium-titanium oxide satisfies Formulae (1) to (3) below in an L*a*b* color space according to Japanese Industrial Standard JIS Z 8722:2009: 95.0?L*?100??(1) ?1.0?a*?1.0??(2) ?1.0?b*?6.0??(3).
    Type: Application
    Filed: February 16, 2023
    Publication date: March 14, 2024
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshiaki MURATA, Kakuya UEDA, Yasuhiro HARADA, Kazuki ISE, Norio TAKAMI
  • Publication number: 20240079576
    Abstract: A niobium-titanium-based oxide includes niobium-titanium-based oxide particles, wherein an Si2p peak area and an Nb3d peak area, as measured by X-ray photoelectron spectroscopy for the niobium-titanium-based oxide particles, satisfy a ratio A of 0.40?A?1.0, provided that the ratio A is the Si2p peak area/the Nb3d peak area.
    Type: Application
    Filed: August 30, 2023
    Publication date: March 7, 2024
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kakuya UEDA, Yoshiaki MURATA, Yasuhiro HARADA, Norio TAKAMI, Shinsuke MATSUNO
  • Publication number: 20200020799
    Abstract: A semiconductor device capable of reducing the influence of noise and easily securing a breakdown voltage between a source wiring and a drain wiring constituting a capacitance between a source and a drain even when shrinkage of a cell progresses, and a manufacturing method thereof are provided. The drain wiring is electrically connected to a substrate region, and the drain wiring is disposed in contact with an upper surface of an interlayer insulating layer. The source wiring is electrically connected to source regions and are disposed in contact with the upper surface of the interlayer insulating layer. A plurality of MOSFET cells are arranged side by side in a X-direction. The drain wiring and the source wiring extends in the X direction and are adjacent to each other in a Y direction crossing the X direction to form a capacitor.
    Type: Application
    Filed: June 19, 2019
    Publication date: January 16, 2020
    Inventors: Yoshiaki UEDA, Satoru TOKUDA, Satoshi UCHIYA, Hiroyoshi KUDOU
  • Patent number: 9320636
    Abstract: A support device includes: a force measurement sensor structure which includes a shaft having first and second end sections, an intermediate element movably provided between the first and second end sections, first and second elastic members respectively provided between the first end section and the intermediate element and between the second end section and the intermediate element, a linear potentiometer detecting the one dimensional direction position of the intermediate element, and a gripping unit transmitting a force to the intermediate element in an interlocking manner with movement of upper or lower limb; a drive unit changing a load applied to the intermediate element; a control unit controlling the drive unit; and a wearable unit including a front frame provided on a front side of a user, a rear frame connected to the front frame, provided on a rear side of the user, and supporting the drive unit, and an arm suspending a wire which connects the force measurement sensor structure and the drive unit,
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: April 26, 2016
    Assignee: Panasonic Corporation
    Inventors: Go Shirogauchi, Hiromichi Fujimoto, Yoshiaki Ueda, Makoto Konishi
  • Publication number: 20150190261
    Abstract: A support device includes: a force measurement sensor structure which includes a shaft having first and second end sections, an intermediate element movably provided between the first and second end sections, first and second elastic members respectively provided between the first end section and the intermediate element and between the second end section and the intermediate element, a linear potentiometer detecting the one dimensional direction position of the intermediate element, and a gripping unit transmitting a force to the intermediate element in an interlocking manner with movement of upper or lower limb; a drive unit changing a load applied to the intermediate element; a control unit controlling the drive unit; and a wearable unit including a front frame provided on a front side of a user, a rear frame connected to the front frame, provided on a rear side of the user, and supporting the drive unit, and an arm suspending a wire which connects the force measurement sensor structure and the drive unit,
    Type: Application
    Filed: June 25, 2013
    Publication date: July 9, 2015
    Inventors: Go Shirogauchi, Hiromichi Fujimoto, Yoshiaki Ueda, Makoto Konishi
  • Patent number: 8847381
    Abstract: A semiconductor element housing package includes a substrate, a frame body disposed on the substrate; an insulating substrate disposed in a frame-body-surrounded region of the substrate; a first mounting member disposed on the insulating substrate, for mounting a power semiconductor element thereon; a second mounting member disposed on the insulating substrate so as to be spaced away from the first mounting member; a first lead member having a first bend; and a second lead member having a second bend. The first lead member is disposed so as to pass through the frame body from an exterior thereof and extend over the first mounting member and makes connection therewith through the first bend. The second lead member is disposed so as to pass through the frame body from the exterior thereof and extend over the second mounting member and makes connection therewith through the second bend.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: September 30, 2014
    Assignee: Kyocera Corporation
    Inventors: Yoshiaki Ueda, Shinji Nakamoto, Hiroshi Mizushima, Nobuyuki Tanaka
  • Patent number: 8837164
    Abstract: There are provided a substrate for mounting a device and a package for housing the device employing the same in which a power semiconductor device can be readily set for a temperature suitable for operation and can thus function in a proper fashion. The substrate for mounting the device includes a support body having, on one main surface of the support body, a device mounting portion for mounting a power semiconductor device, the support body having a plurality of columnar parts that are spaced apart in a thickness direction with respect to the device mounting portion and are arranged apart from each other; and a heat accumulating region which is disposed between the columnar parts and is lower in thermal conductivity than the support body.
    Type: Grant
    Filed: January 22, 2010
    Date of Patent: September 16, 2014
    Assignee: Kyocera Corporation
    Inventors: Kazuhiro Kawabata, Kiyoshige Miyawaki, Yoshiaki Ueda, Shinji Nakamoto, Tsutomu Sugimoto
  • Publication number: 20130307135
    Abstract: A semiconductor element housing package includes a substrate, a frame body disposed on the substrate; an insulating substrate disposed in a frame-body-surrounded region of the substrate; a first mounting member disposed on the insulating substrate, for mounting a power semiconductor element thereon; a second mounting member disposed on the insulating substrate so as to be spaced away from the first mounting member; a first lead member having a first bend; and a second lead member having a second bend. The first lead member is disposed so as to pass through the frame body from an exterior thereof and extend over the first mounting member and makes connection therewith through the first bend. The second lead member is disposed so as to pass through the frame body from the exterior thereof and extend over the second mounting member and makes connection therewith through the second bend.
    Type: Application
    Filed: December 19, 2011
    Publication date: November 21, 2013
    Applicant: KYOCERA CORPORATION
    Inventors: Yoshiaki Ueda, Shinji Nakamoto, Hiroshi Mizushima, Nobuyuki Tanaka
  • Patent number: 8450842
    Abstract: A structure includes a circuit substrate including a first substrate and a second substrate. The first substrate has a region where an electronic component is to be mounted. The second substrate has a side surface connected to a first side surface of the first substrate. The structure further includes a frame on the circuit substrate, enclosing the region in a plane view. The frame crosses the boundary between the first substrate and the second substrate.
    Type: Grant
    Filed: March 20, 2008
    Date of Patent: May 28, 2013
    Assignee: KYOCERA Corporation
    Inventor: Yoshiaki Ueda
  • Patent number: 8405200
    Abstract: An electronic-component-housing package comprises a container including a rectangular mount on which an electronic component is to be mounted and a sidewall surrounding the mount. The electronic-component-housing package comprises a lead terminal extending from an inside of a space enclosed by the sidewall to an outside of the space. A tip part of the lead terminal is extending along one side of the mount.
    Type: Grant
    Filed: March 27, 2008
    Date of Patent: March 26, 2013
    Assignee: Kyocera Corporation
    Inventor: Yoshiaki Ueda
  • Patent number: 8301348
    Abstract: In vehicular control method and apparatus for a shift-by-wire device, a selected shift position is modified to at least one of a vehicular parking position, a neutral position, and a traveling position, the selected shift position is modified to the vehicular parking position when a power switch is switched to an OFF position, and the modification of the shift position to the vehicular parking position is inhibited when an operation pattern of an operation input section while the power switch is in the ON position is made coincident with the operation pattern prescribed as a cipher code which inhibits the shift position modification to the vehicular parking position, the operation patterns being constituted by a combination of operation patterns which would not be carried out in the operation section during an ordinary traveling.
    Type: Grant
    Filed: February 4, 2010
    Date of Patent: October 30, 2012
    Assignee: JATCO Ltd
    Inventors: Fumitaka Nagashima, Yoshiaki Ueda, Ryusuke Oshiro, Tomoyuki Suwabe
  • Patent number: 8242387
    Abstract: An electronic component storing package which generates a large quantity of heat during operation and an electronic apparatus storing such an electronic component are provided. In the electronic component storing package and the electronic apparatus, a heat dissipating member (1) is used which comprising at least five layers including first metal layers (11) having good thermal conductivity and second metal layers (12) having a smaller coefficient of thermal expansion and less thickness compared with the first metal layers (11), the first metal layers (11) and second metal layers (12) being alternately stacked, the first metal layers uppermost and lowermost layers of the layers, a thickness of at least one internally-arranged first metal layer (11a) being thicker than that of the lowermost and uppermost layers.
    Type: Grant
    Filed: July 27, 2007
    Date of Patent: August 14, 2012
    Assignees: Kyocera Corporation, FJ Composite Materials Co., Ltd.
    Inventors: Atsurou Yoneda, Tetsurou Abumita, Yoshiaki Ueda, Eiki Tsushima
  • Publication number: 20110273846
    Abstract: There are provided a substrate for mounting a device and a package for housing the device employing the same in which a power semiconductor device can be readily set for a temperature suitable for operation and can thus function in a proper fashion. The substrate for mounting the device includes a support body having, on one main surface of the support body, a device mounting portion for mounting a power semiconductor device, the support body having a plurality of columnar parts that are spaced apart in a thickness direction with respect to the device mounting portion and are arranged apart from each other; and a heat accumulating region which is disposed between the columnar parts and is lower in thermal conductivity than the support body.
    Type: Application
    Filed: January 22, 2010
    Publication date: November 10, 2011
    Applicant: KYOCERA CORPORATION
    Inventors: Kazuhiro Kawabata, Kiyoshige Miyawaki, Yoshiaki Ueda, Shinji Nakamoto, Tsutomu Sugimo
  • Publication number: 20100206118
    Abstract: In vehicular control method and apparatus for a shift-by-wire device, a selected shift position is modified to at least one of a vehicular parking position, a neutral position, and a traveling position, the selected shift position is modified to the vehicular parking position when a power switch is switched to an OFF position, and the modification of the shift position to the vehicular parking position is inhibited when an operation pattern of an operation input section while the power switch is in the ON position is made coincident with the operation pattern prescribed as a cipher code which inhibits the shift position modification to the vehicular parking position, the operation patterns being constituted by a combination of operation patterns which would not be carried out in the operation section during an ordinary traveling.
    Type: Application
    Filed: February 4, 2010
    Publication date: August 19, 2010
    Inventors: Fumitaka Nagashima, Yoshiaki Ueda, Ryusuke Oshiro, Tomoyuki Suwabe
  • Publication number: 20100200932
    Abstract: An electronic-component-housing package comprises a container including a rectangular mount on which an electronic component is to be mounted and a sidewall surrounding the mount. The electronic-component-housing package comprises a lead terminal extending from an inside of a space enclosed by the sidewall to an outside of the space. A tip part of the lead terminal is extending along one side of the mount.
    Type: Application
    Filed: March 27, 2008
    Publication date: August 12, 2010
    Applicant: KYOCERA CORPORATION
    Inventor: Yoshiaki Ueda
  • Publication number: 20100142643
    Abstract: A multi-carrier signal transmitter includes a multi-carrier modulation circuit, a power converter, a frequency converter and an interference protection determination circuit, and that the interference protection determination circuit determines a difference in power levels between a higher layer component and a lower layer component of multi-carrier signals in a manner to avoid digital interference. The power converter converts a power level of the multi-carrier signals when necessary based on a data of the determination, and the frequency converter converts a center frequency band of the multi-carrier signals when necessary based on the data of the determination. The digital interference of the hierarchical multi-carrier signals can be prevented.
    Type: Application
    Filed: July 24, 2008
    Publication date: June 10, 2010
    Applicant: Panasonic Corporation
    Inventors: Yoshiaki Ueda, Hideki Takahashi
  • Publication number: 20100059271
    Abstract: An electronic component storing package which generates a large quantity of heat during operation and an electronic apparatus storing such an electronic component are provided. In the electronic component storing package and the electronic apparatus, a heat dissipating member (1) is used which comprising at least five layers including first metal layers (11) having good thermal conductivity and second metal layers (12) having a smaller coefficient of thermal expansion and less thickness compared with the first metal layers (11), the first metal layers (11) and second metal layers (12) being alternately stacked, the first metal layers uppermost and lowermost layers of the layers, a thickness of at least one internally-arranged first metal layer (11a) being thicker than that of the lowermost and uppermost layers.
    Type: Application
    Filed: July 27, 2007
    Publication date: March 11, 2010
    Applicants: KYOCERA CORPORATION, FJ COMPOSITE MATERIALS CO., LTD.
    Inventors: Atsurou Yoneda, Tetsurou Abumita, Yoshiaki Ueda, Eiki Tsushima
  • Patent number: 7525049
    Abstract: A battery case as an electronic component case includes a second conductive plate made of metal, an insulating wall having an upper end surface and a bottom end surface, a first conductive plate made of metal joined to an upper end surface of the insulating wall, and a second conductive plate attached to the bottom end surface of the insulating wall. The insulating wall has a first conductor layer formed on an entire perimeter of the upper end surface thereof and a second conductor layer formed on an entire perimeter of a lower surface thereof, an electrode formed at a peripheral portion of the lower surface of the insulating wall so as to be electrically independent from the second conductor layer, an external connection terminal brazed to the electrode, and a connection conductor formed from the first conductor layer to the electrode. The first conductive plate is attached to the insulating wall via the first conductor layer.
    Type: Grant
    Filed: August 25, 2005
    Date of Patent: April 28, 2009
    Assignee: Kyocera Corporation
    Inventors: Manabu Miyaishi, Yoshiaki Ueda, Yoshihiro Ushio
  • Publication number: 20080230890
    Abstract: A structure includes a circuit substrate including a first substrate and a second substrate. The first substrate has a region where an electronic component is to be mounted. The second substrate has a side surface connected to a first side surface of the first substrate. The structure further includes a frame on the circuit substrate, enclosing the region in a plane view. The frame crosses the boundary between the first substrate and the second substrate.
    Type: Application
    Filed: March 20, 2008
    Publication date: September 25, 2008
    Applicant: KYOCERA CORPORATION
    Inventor: Yoshiaki UEDA