Patents by Inventor Yoshiharu Kanegae

Yoshiharu Kanegae has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9503018
    Abstract: A semiconductor device is formed by sealing, with a resin, a semiconductor chip (CP1) having an oscillation circuit utilizing a reference resistor. The oscillation circuit generates a reference current by utilizing the reference resistor, a voltage is generated in accordance with this reference current and an oscillation frequency of the oscillation unit, and the oscillation unit oscillates at a frequency in accordance with the generated voltage.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: November 22, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Toshiaki Tsutsumi, Yoshihiro Funato, Tomonori Okudaira, Tadato Yamagata, Akihisa Uchida, Takeshi Terasaki, Tomohisa Suzuki, Yoshiharu Kanegae
  • Publication number: 20160142011
    Abstract: A semiconductor device is formed by sealing, with a resin, a semiconductor chip (CP1) having an oscillation circuit utilizing a reference resistor. The oscillation circuit generates a reference current by utilizing the reference resistor, a voltage is generated in accordance with this reference current and an oscillation frequency of the oscillation unit, and the oscillation unit oscillates at a frequency in accordance with the generated voltage.
    Type: Application
    Filed: November 17, 2015
    Publication date: May 19, 2016
    Inventors: Toshiaki TSUTSUMI, Yoshihiro FUNATO, Tomonori OKUDAIRA, Tadato YAMAGATA, Akihisa UCHIDA, Takeshi TERASAKI, Tomohisa SUZUKI, Yoshiharu KANEGAE
  • Patent number: 9252793
    Abstract: A semiconductor device is formed by sealing, with a resin, a semiconductor chip (CP1) having an oscillation circuit utilizing a reference resistor. The oscillation circuit generates a reference current by utilizing the reference resistor, a voltage is generated in accordance with this reference current and an oscillation frequency of the oscillation unit, and the oscillation unit oscillates at a frequency in accordance with the generated voltage.
    Type: Grant
    Filed: November 29, 2010
    Date of Patent: February 2, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Toshiaki Tsutsumi, Yoshihiro Funato, Tomonori Okudaira, Tadato Yamagata, Akihisa Uchida, Takeshi Terasaki, Tomohisa Suzuki, Yoshiharu Kanegae
  • Patent number: 8816478
    Abstract: Disclosed herein is a device that includes: a semiconductor substrate having a first surface on which a plurality of circuit elements are formed and a second surface opposite to the first surface; an insulating layer covering the second surface of the semiconductor substrate; and a penetration electrode having a body section that penetrates through the semiconductor substrate and a protruding section that is connected to one end of the body section and protrudes from the second surface of the semiconductor substrate. The second surface of the semiconductor substrate is covered with the protruding section of the penetration electrode without intervention of the insulating layer.
    Type: Grant
    Filed: January 8, 2013
    Date of Patent: August 26, 2014
    Assignee: PS4 Luxco S.A.R.L.
    Inventors: Yoshiharu Kanegae, Hisashi Tanie, Mitsuhisa Watanabe, Keiyo Kusanagi
  • Publication number: 20130314165
    Abstract: A semiconductor device is formed by sealing, with a resin, a semiconductor chip (CP1) having an oscillation circuit utilizing a reference resistor. The oscillation circuit generates a reference current by utilizing the reference resistor, a voltage is generated in accordance with this reference current and an oscillation frequency of the oscillation unit, and the oscillation unit oscillates at a frequency in accordance with the generated voltage.
    Type: Application
    Filed: November 29, 2010
    Publication date: November 28, 2013
    Inventors: Toshiaki Tsutsumi, Yoshihiro Funato, Tomonori Okudaira, Tadato Yamagata, Akihisa Uchida, Takeshi Terasaki, Tomohisa Suzuki, Yoshiharu Kanegae
  • Patent number: 8488277
    Abstract: A magnetic recording medium for a hard disk drive, including a thermal conduction layer made of materials having different thermal conductivities formed on a recording layer having data recording regions and including magnetic particles that are heated and cooled for magnetic recording, is provided based on a thermally assisted magnetic recording technique. First thin films made of a material high in thermal conductivity are formed on portions of the thermal conduction layer, said portions located in association with portions of the data recording regions. Second thin films made of a material lower in thermal conductivity than the first thin films are formed between respective pairs of the first thin films within the thermal conduction layer. The magnetic recording medium ensures the thermal stability of the magnetic particles heated for the magnetic recording, and the thermal stability of magnetic particles located near the heated magnetic particles, thereby suppressing disappearance of data.
    Type: Grant
    Filed: January 14, 2010
    Date of Patent: July 16, 2013
    Assignee: Hitachi, Ltd.
    Inventor: Yoshiharu Kanegae
  • Publication number: 20120064374
    Abstract: Disclosed herein are a dot-patterned structure for magnetic recording bits and a magnetic recording medium provided therewith. The former exhibits high functionality and high performance owing to good crystallinity. The dot-patterned structure is composed of a first layer, which is continuous, and a second layer, which is discrete. The magnetic recording medium having a dot-patterned recording layer is formed by the steps of treating an underlying layer by lithography, thereby forming grooves, filling the grooves by epitaxial growth with the same material as the underlying layer, removing the photoresist used for lithography in a solvent, thereby forming pits, and filling the pits by epitaxial growth with a magnetic film as the recording layer.
    Type: Application
    Filed: November 21, 2011
    Publication date: March 15, 2012
    Inventor: Yoshiharu Kanegae
  • Publication number: 20100177426
    Abstract: A magnetic recording medium for a hard disk drive is provided based on a thermally assisted magnetic recording technique. The magnetic recording medium includes a recording layer and a thermal conduction layer. The thermal conduction layer is formed on the recording layer. The thermal conduction layer is made of materials having different thermal conductivities. The recording layer has data recording regions. First thin films made of a material highest in thermal conductivity among the materials are formed on some portions of the thermal conduction layer, with the some portions being located in association with portions of the data recording regions included in the recording layer. Second thin films made of a material relatively lower in thermal conductivity than the first thin films are formed between respective pairs of the first thin films within the thermal conduction layer. The recording layer includes magnetic particles that are heated and cooled for magnetic recording.
    Type: Application
    Filed: January 14, 2010
    Publication date: July 15, 2010
    Inventor: Yoshiharu KANEGAE
  • Publication number: 20090098413
    Abstract: Disclosed herein are a dot-patterned structure for magnetic recording bits and a magnetic recording medium provided therewith. The former exhibits high functionality and high performance owing to good crystallinity. The dot-patterned structure is composed of a first layer, which is continuous, and a second layer, which is discrete. The magnetic recording medium having a dot-patterned recording layer is formed by the steps of treating an underlying layer by lithography, thereby forming grooves, filling the grooves by epitaxial growth with the same material as the underlying layer, removing the photoresist used for lithography in a solvent, thereby forming pits, and filling the pits by epitaxial growth with a magnetic film as the recording layer.
    Type: Application
    Filed: October 10, 2008
    Publication date: April 16, 2009
    Inventor: Yoshiharu KANEGAE
  • Patent number: 7279739
    Abstract: There is provided a high-reliability nano-dots memory by forming the nano dots uniformly. Also, there is provided the high-speed and high-reliability nano-dots memory by employing a silicon-oxide-film alternative material as a tunnel insulating film. The nano-dots memory includes the tunnel insulating film and silicide nano-dots of CoSi2 or NiSi2. Here, the tunnel insulating film is formed by epitaxially growing a high-permittivity insulating film of HfO2, ZrO2 or CeO2 on a silicon or germanium substrate, or preferably, on a silicon or germanium (111) substrate. Also, the silicide nano-dots are formed on the tunnel insulating film.
    Type: Grant
    Filed: February 15, 2006
    Date of Patent: October 9, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Yoshiharu Kanegae, Tomio Iwasaki
  • Publication number: 20070126051
    Abstract: A semiconductor memory device having a stable characteristic and high reliability is achieved with formation of nano-dots with excellent interface stability. Source/drain diffusion layers are formed on a P-type silicon substrate to form a silicon oxide film. On this silicon oxide film, a silicon-rich oxide film is formed in a dot shape. On the silicon-rich oxide film, an interlayer dielectric made of SiO2 is formed. The silicon-rich oxide film has a property of storing charges in the film and excellent in stability of an interface with a silicon oxide film used for a tunneling dielectric. With this, a semiconductor memory device having a stable characteristic and high reliability is achieved with formation of nano-dots with excellent interface stability.
    Type: Application
    Filed: December 6, 2006
    Publication date: June 7, 2007
    Applicant: Hitachi, Ltd.
    Inventor: Yoshiharu Kanegae
  • Patent number: 7215566
    Abstract: A magnetic memory includes a TMR element in its memory layer, wherein the TMR element in the memory layer has ferromagnetic layers which are kept in tensile strain, the ferromagnetic layers having either Fe, Co or Ni, and a wiring layer adjacent to each of the ferromagnetic layers includes either Ru, W, Ir, Os or Mo, thereby increasing the magnetization.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: May 8, 2007
    Assignee: Hitachi, Ltd.
    Inventor: Yoshiharu Kanegae
  • Patent number: 7180143
    Abstract: A semiconductor device constitutes an electric field effect type transistor having a semiconductor substrate, a gate insulating layer formed on the substrate and a gate electrode formed on the gate insulating layer. The gate insulating layer is mainly formed of silicon oxynitride (SiON) and a strain state of the gate insulating layer is a compressed strain state.
    Type: Grant
    Filed: August 4, 2004
    Date of Patent: February 20, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Yoshiharu Kanegae, Tomio Iwasaki, Hiroshi Moriya
  • Publication number: 20060180852
    Abstract: There is provided a high-reliability nano-dots memory by forming the nano dots uniformly. Also, there is provided the high-speed and high-reliability nano-dots memory by employing a silicon-oxide-film alternative material as a tunnel insulating film. The nano-dots memory includes the tunnel insulating film and silicide nano-dots of CoSi2 or NiSi2. Here, the tunnel insulating film is formed by epitaxially growing a high-permittivity insulating film of HfO2, ZrO2 or CeO2 on a silicon or germanium substrate, or preferably, on a silicon or germanium (111) substrate. Also, the silicide nano-dots are formed on the tunnel insulating film.
    Type: Application
    Filed: February 15, 2006
    Publication date: August 17, 2006
    Inventors: Yoshiharu Kanegae, Tomio Iwasaki
  • Publication number: 20060114714
    Abstract: A magnetic memory includes a TMR element in its memory layer, wherein the TMR element in the memory layer has ferromagnetic layers which are kept in tensile strain, the ferromagnetic layers having either Fe, Co or Ni, and a wiring layer adjacent to each of the ferromagnetic layers includes either Ru, W, Ir, Os or Mo, thereby increasing the magnetization.
    Type: Application
    Filed: August 31, 2005
    Publication date: June 1, 2006
    Inventor: Yoshiharu Kanegae
  • Publication number: 20050051855
    Abstract: A semiconductor device constitutes an electric field effect type transistor having a semiconductor substrate, a gate insulating layer formed on the substrate and a gate electrode formed on the gate insulating layer. The gate insulating layer is mainly formed of silicon oxynitride (SiON) and a strain state of the gate insulating layer is a compressed strain state.
    Type: Application
    Filed: August 4, 2004
    Publication date: March 10, 2005
    Inventors: Yoshiharu Kanegae, Tomio Iwasaki, Hiroshi Moriya