Patents by Inventor Yoshiharu Ogata

Yoshiharu Ogata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8749041
    Abstract: A semiconductor device includes a first semiconductor chip that is mounted face-down on a substrate, a second semiconductor chip that is mounted face-up on the first semiconductor chip, and a dummy chip that is interposed between the first semiconductor chip and the second semiconductor chip. The dummy chip is made from a homogenous material comprising silicon or an alloy containing an atomic percentage majority of silicon.
    Type: Grant
    Filed: May 19, 2010
    Date of Patent: June 10, 2014
    Assignee: Seiko Epson Corporation
    Inventors: Yoshiharu Ogata, Tadashi Aizawa, Takeo Kitazawa
  • Patent number: 8368233
    Abstract: A semiconductor device comprises a wiring substrate including a wiring pattern; a semiconductor chip installed on the wiring substrate, including a plurality of pads formed on a surface of the semiconductor chip, which opposes the wiring substrate; a first resin layer covering over a part of the wiring pattern within a region of overlapping the semiconductor chip; and a second resin layer installed between the semiconductor chip and the first resin layer. The pads are oppose to and coupled with a part of the wiring pattern exposed over the first resin layer; and the linear expansion coefficient of the wiring substrate is larger than that of the semiconductor chip, the elastic modulus of the wiring substrate is lower than that of the semiconductor chip and the linear expansion coefficient of the first resin layer is larger than that of the second resin layer. The elastic modulus of the first resin layer is lower than that of the second resin layer.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: February 5, 2013
    Assignee: Seiko Epson Corporation
    Inventor: Yoshiharu Ogata
  • Publication number: 20110241221
    Abstract: A semiconductor device comprises a wiring substrate including a wiring pattern; a semiconductor chip installed on the wiring substrate, including a plurality of pads formed on a surface of the semiconductor chip, which opposes the wiring substrate; a first resin layer covering over a part of the wiring pattern within a region of overlapping the semiconductor chip; and a second resin layer installed between the semiconductor chip and the first resin layer. The pads are oppose to and coupled with a part of the wiring pattern exposed over the first resin layer; and the linear expansion coefficient of the wiring substrate is larger than that of the semiconductor chip, the elastic modulus of the wiring substrate is lower than that of the semiconductor chip and the linear expansion coefficient of the first resin layer is larger than that of the second resin layer. The elastic modulus of the first resin layer is lower than that of the second resin layer.
    Type: Application
    Filed: June 14, 2011
    Publication date: October 6, 2011
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Yoshiharu OGATA
  • Patent number: 7982319
    Abstract: A semiconductor device comprises a wiring substrate including a wiring pattern; a semiconductor chip installed on the wiring substrate, including a plurality of pads formed on a surface of the semiconductor chip, which opposes the wiring substrate; a first resin layer covering over a part of the wiring pattern within a region of overlapping the semiconductor chip; and a second resin layer installed between the semiconductor chip and the first resin layer. The pads are oppose to and coupled with a part of the wiring pattern exposed over the first resin layer; and the linear expansion coefficient of the wiring substrate is larger than that of the semiconductor chip, the elastic modulus of the wiring substrate is lower than that of the semiconductor chip and the linear expansion coefficient of the first resin layer is larger than that of the second resin layer. The elastic modulus of the first resin layer is lower than that of the second resin layer.
    Type: Grant
    Filed: December 14, 2009
    Date of Patent: July 19, 2011
    Assignee: Seiko Epson Corporation
    Inventor: Yoshiharu Ogata
  • Publication number: 20100230827
    Abstract: A semiconductor device includes a first semiconductor chip that is mounted face-down on a substrate, a second semiconductor chip that is mounted face-up on the first semiconductor chip, and a dummy chip that is interposed between the first semiconductor chip and the second semiconductor chip. The dummy chip is made from a homogenous material comprising silicon or an alloy containing an atomic percentage majority of silicon.
    Type: Application
    Filed: May 19, 2010
    Publication date: September 16, 2010
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Yoshiharu OGATA, Tadashi AIZAWA, Takeo KITAZAWA
  • Publication number: 20100090327
    Abstract: A semiconductor device comprises a wiring substrate including a wiring pattern; a semiconductor chip installed on the wiring substrate, including a plurality of pads formed on a surface of the semiconductor chip, which opposes the wiring substrate; a first resin layer covering over a part of the wiring pattern within a region of overlapping the semiconductor chip; and a second resin layer installed between the semiconductor chip and the first resin layer. The pads are oppose to and coupled with a part of the wiring pattern exposed over the first resin layer; and the linear expansion coefficient of the wiring substrate is larger than that of the semiconductor chip, the elastic modulus of the wiring substrate is lower than that of the semiconductor chip and the linear expansion coefficient of the first resin layer is larger than that of the second resin layer. The elastic modulus of the first resin layer is lower than that of the second resin layer.
    Type: Application
    Filed: December 14, 2009
    Publication date: April 15, 2010
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Yoshiharu OGATA
  • Patent number: 7656026
    Abstract: A semiconductor device, includes: a wiring substrate having a wiring pattern on a front surface thereof; a first semiconductor chip mounted on the front surface of the wiring substrate; a first heat radiator having a first recess housing the first semiconductor chip and making contact with the front surface of the wiring substrate and the first semiconductor chip directly or with a first insulation layer; a second heat radiator making contact with a rear surface of the wiring substrate directly or with a second insulation layer; and a first fixing member passing through the first heat radiator, the wiring substrate, and the second heat radiator, and pressing the first heat radiator and the second heat radiator to the wiring substrate.
    Type: Grant
    Filed: July 7, 2008
    Date of Patent: February 2, 2010
    Assignee: Seiko Epson Corporation
    Inventors: Yoshiharu Ogata, Yoshikatsu Soma, Hiroharu Kondo, Munehide Saimen
  • Patent number: 7656044
    Abstract: A semiconductor device comprises a wiring substrate including a wiring pattern; a semiconductor chip installed on the wiring substrate, including a plurality of pads formed on a surface of the semiconductor chip, which opposes the wiring substrate; a first resin layer covering over a part of the wiring pattern within a region of overlapping the semiconductor chip; and a second resin layer installed between the semiconductor chip and the first resin layer. The pads are oppose to and coupled with a part of the wiring pattern exposed over the first resin layer; and the linear expansion coefficient of the wiring substrate is larger than that of the semiconductor chip, the elastic modulus of the wiring substrate is lower than that of the semiconductor chip and the linear expansion coefficient of the first resin layer is larger than that of the second resin layer. The elastic modulus of the first resin layer is lower than that of the second resin layer.
    Type: Grant
    Filed: July 16, 2008
    Date of Patent: February 2, 2010
    Assignee: Seiko Epson Corporation
    Inventor: Yoshiharu Ogata
  • Patent number: 7569922
    Abstract: A semiconductor device includes: a first semiconductor chip face-down mounted on a substrate; a second semiconductor chip face-up mounted on the first semiconductor chip; an electromagnetic shielding plate inserted between the first semiconductor chip and the second semiconductor chip; and a bonding wire bonded on the substrate so as to be astride of the electromagnetic shielding plate.
    Type: Grant
    Filed: August 8, 2007
    Date of Patent: August 4, 2009
    Assignee: Seiko Epson Corporation
    Inventor: Yoshiharu Ogata
  • Patent number: 7521293
    Abstract: A method of manufacturing a semiconductor device uses a substrate on which an interconnect pattern is formed and on which a protective film is formed to include an opening and to cover the interconnect pattern in a region other than the opening. The method includes: attaching an adhesive sheet to an area including the opening and a boundary between the opening and the protective film so that a void is formed due to a level difference between the interconnect pattern and the substrate; softening the adhesive sheet by heating; and causing a semiconductor chip to adhere to the substrate through the adhesive sheet. The protective film includes a groove which connects with the opening, the adhesive sheet is attached except a part of the groove, and the void is discharged through the groove by heating and softening the adhesive sheet.
    Type: Grant
    Filed: September 9, 2004
    Date of Patent: April 21, 2009
    Assignee: Seiko Epson Corporation
    Inventor: Yoshiharu Ogata
  • Publication number: 20090020867
    Abstract: A semiconductor device, includes: a wiring substrate having a wiring pattern on a front surface thereof; a first semiconductor chip mounted on the front surface of the wiring substrate; a first heat radiator having a first recess housing the first semiconductor chip and making contact with the front surface of the wiring substrate and the first semiconductor chip directly or with a first insulation layer; a second heat radiator making contact with a rear surface of the wiring substrate directly or with a second insulation layer; and a first fixing member passing through the first heat radiator, the wiring substrate, and the second heat radiator, and pressing the first heat radiator and the second heat radiator to the wiring substrate.
    Type: Application
    Filed: July 7, 2008
    Publication date: January 22, 2009
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Yoshiharu OGATA, Yoshikatsu SOMA, Hiroharu KONDO, Munehide SAIMEN
  • Patent number: 7476975
    Abstract: A semiconductor device comprises a wiring substrate including a wiring pattern; a semiconductor chip installed on the wiring substrate, including a plurality of pads formed on a surface of the semiconductor chip, which opposes the wiring substrate; a first resin layer covering over a part of the wiring pattern within a region of overlapping the semiconductor chip; and a second resin layer installed between the semiconductor chip and the first resin layer. The pads are oppose to and coupled with a part of the wiring pattern exposed over the first resin layer; and the linear expansion coefficient of the wiring substrate is larger than that of the semiconductor chip, the elastic modulus of the wiring substrate is lower than that of the semiconductor chip and the linear expansion coefficient of the first resin layer is larger than that of the second resin layer. The elastic modulus of the first resin layer is lower than that of the second resin layer.
    Type: Grant
    Filed: July 7, 2005
    Date of Patent: January 13, 2009
    Assignee: Seiko Epson Corporation
    Inventor: Yoshiharu Ogata
  • Publication number: 20080277803
    Abstract: A semiconductor device comprises a wiring substrate including a wiring pattern; a semiconductor chip installed on the wiring substrate, including a plurality of pads formed on a surface of the semiconductor chip, which opposes the wiring substrate; a first resin layer covering over a part of the wiring pattern within a region of overlapping the semiconductor chip; and a second resin layer installed between the semiconductor chip and the first resin layer. The pads are oppose to and coupled with a part of the wiring pattern exposed over the first resin layer; and the linear expansion coefficient of the wiring substrate is larger than that of the semiconductor chip, the elastic modulus of the wiring substrate is lower than that of the semiconductor chip and the linear expansion coefficient of the first resin layer is larger than that of the second resin layer. The elastic modulus of the first resin layer is lower than that of the second resin layer.
    Type: Application
    Filed: July 16, 2008
    Publication date: November 13, 2008
    Applicant: Seiko Epson Corporation
    Inventor: Yoshiharu OGATA
  • Publication number: 20080274588
    Abstract: A method of fabricating a semiconductor device, including: preparing a wiring board on which is mounted a first semiconductor chip having a plurality of first pads; electrically connecting each of the first pads to an interconnecting pattern of the first semiconductor chip by a wire; providing resin paste on the first semiconductor chip; mounting a second semiconductor chip having a plurality of second pads on the first semiconductor chip with the resin paste interposed therebetween; and forming a spacer by hardening the resin paste to fix the first and second semiconductor chips together, wherein the spacer is formed to extend under the second pads and further outward; and wherein the highest portion of the wire is disposed on the outer side of the first semiconductor chip.
    Type: Application
    Filed: June 27, 2008
    Publication date: November 6, 2008
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Yoshiharu Ogata
  • Patent number: 7410827
    Abstract: A method of fabricating a semiconductor device, including: preparing a wiring board on which is mounted a first semiconductor chip having a plurality of first pads; electrically connecting each of the first pads to an interconnecting pattern of the first semiconductor chip by a wire; providing resin paste on the first semiconductor chip; mounting a second semiconductor chip having a plurality of second pads on the first semiconductor chip with the resin paste interposed therebetween; and forming a spacer by hardening the resin paste to fix the first and second semiconductor chips together, wherein the spacer is formed to extend under the second pads and further outward; and wherein the highest portion of the wire is disposed on the outer side of the first semiconductor chip.
    Type: Grant
    Filed: January 13, 2006
    Date of Patent: August 12, 2008
    Assignee: Seiko Epson Corporation
    Inventor: Yoshiharu Ogata
  • Publication number: 20070296087
    Abstract: A semiconductor device includes a first semiconductor chip face-down mounted on a substrate, a second semiconductor chip face-up mounted on the first semiconductor chip, and an electromagnetic shielding plate interposed between the first semiconductor chip and the second semiconductor chip.
    Type: Application
    Filed: August 16, 2007
    Publication date: December 27, 2007
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Yoshiharu OGATA, Tadashi AIZAWA, Takeo KITAZAWA
  • Publication number: 20070278646
    Abstract: A semiconductor device includes: a first semiconductor chip face-down mounted on a substrate; a second semiconductor chip face-up mounted on the first semiconductor chip; an electromagnetic shielding plate inserted between the first semiconductor chip and the second semiconductor chip; and a bonding wire bonded on the substrate so as to be astride of the electromagnetic shielding plate.
    Type: Application
    Filed: August 8, 2007
    Publication date: December 6, 2007
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Yoshiharu Ogata
  • Patent number: 7179687
    Abstract: A method of manufacturing a semiconductor device is provided including depressing a bonding tool having a concave portion toward a wiring board with a semiconductor chip disposed within the concave portion, pressing the semiconductor chip with a bottom face of the concave portion, fluidizing a resin provided between the semiconductor chip and the wiring board, and filling a lateral space proximate the semiconductor chip within the concave portion with the resin, and curing the resin.
    Type: Grant
    Filed: October 26, 2004
    Date of Patent: February 20, 2007
    Assignee: Seiko Epson Corporation
    Inventor: Yoshiharu Ogata
  • Patent number: 7154188
    Abstract: A semiconductor chip includes a semiconductor substrate including first and second surfaces and a plurality of side surfaces, the first and second surfaces being parallel to each other and facing in opposite directions, the side surfaces connecting peripheries of the first and second surfaces. At least one of the side surfaces is an inclined surface with respect to the first and second surfaces, and a groove is formed in the inclined surface. The groove extends in a direction which intersects a plane parallel to the first and second surfaces and extends in a direction which intersects a plane which intersects the first and second surfaces at right angles.
    Type: Grant
    Filed: October 22, 2004
    Date of Patent: December 26, 2006
    Assignee: Seiko Epson Corporation
    Inventor: Yoshiharu Ogata
  • Publication number: 20060115930
    Abstract: A method of fabricating a semiconductor device, including: preparing a wiring board on which is mounted a first semiconductor chip having a plurality of first pads; electrically connecting each of the first pads to an interconnecting pattern of the first semiconductor chip by a wire; providing resin paste on the first semiconductor chip; mounting a second semiconductor chip having a plurality of second pads on the first semiconductor chip with the resin paste interposed therebetween; and forming a spacer by hardening the resin paste to fix the first and second semiconductor chips together, wherein the spacer is formed to extend under the second pads and further outward; and wherein the highest portion of the wire is disposed on the outer side of the first semiconductor chip.
    Type: Application
    Filed: January 13, 2006
    Publication date: June 1, 2006
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Yoshiharu Ogata