Patents by Inventor Yoshihiko Hirai

Yoshihiko Hirai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20010006408
    Abstract: In an orientation division type liquid crystal display device for widen a viewing angle of a display pixel of an active matrix type liquid crystal color display device having a COT structure, pixel color layers (6B, 6R, 6G) as color filters and pixel electrodes 3 are formed on a substrate on the side of the pixel electrodes and slopes 13 are provided along four side peripheries of each pixel electrode. Liquid crystal molecules 8 between each pixel electrode of the pixel electrode substrate and a common electrode of an opposing substrate are controlled in orientation direction along the slopes to divide it to a plurality of directions to thereby widen a viewing angle of a pixel display.
    Type: Application
    Filed: December 20, 2000
    Publication date: July 5, 2001
    Inventors: Hiroaki Matsuyama, Kiyomi Kawada, Seiji Suzuki, Yoshihiko Hirai, Michiaki Sakamoto, Mamoru Okamoto, Yuji Yamamoto, Toshiya Ishii, Teruaki Suzuki, Ken Sumiyoshi, Masayoshi Suzuki
  • Patent number: 6256082
    Abstract: This invention provide a liquid crystal display comprising a liquid crystal layer between two substrates each of which has an electrode, wherein the liquid crystal layer concomitantly has at least two micro-regions, and the electrode on one of the substrates has an opening, in the region of which there is provided a second electrode for controlling the initial orientation of the liquid crystal. The liquid crystal display has improved properties such as high contrast, quick response and excellent properties for an angle of visibility and can be manufactured without troublesome steps such as a photoresist step.
    Type: Grant
    Filed: October 5, 1998
    Date of Patent: July 3, 2001
    Assignee: NEC Corporation
    Inventors: Masayoshi Suzuki, Hideya Murai, Toshiya Ishii, Yoshihiko Hirai, Kazumi Kobayashi, Hiroaki Matsuyama, Daisuke Inoue
  • Publication number: 20010004274
    Abstract: A VA (Vertical Aligned) type active-matrix liquid crystal display capable of stabilizing a boundary position between divided areas (alignment areas). The liquid crystal display comprises a TFT (thin film transistor) substrate including a pixel electrode provided for each pixel and a driving element such as a TFT provided for each pixel electrode, an opposite substrate disposed opposite to the TFT substrate and including an opposite electrode, and a liquid crystal layer sandwiched between the TFT substrate and the opposite substrate. Each pixel electrode has a recess in groove shape formed therein. The pixel electrode preferably has a generally rectangular shape. The recess is provided such that it extends from one of a pair of opposite sides of the pixel electrode to the other to divide the pixel electrode into two parts.
    Type: Application
    Filed: December 18, 2000
    Publication date: June 21, 2001
    Applicant: NEC Corporation
    Inventors: Michiaki Sakamoto, Yuji Yamamoto, Mamoru Okamoto, Masayoshi Suzuki, Toshiya Ishii, Teruaki Suzuki, Hiroaki Matsuyama, Kiyomi Kawada, Seiji Suzuki, Yoshihiko Hirai
  • Patent number: 6103583
    Abstract: A quantization functional device includes: a silicon thin layer having a first surface and a second surface each made of a predetermined crystal surface, and the silicon thin layer being formed of single crystalline silicon having a thickness sufficiently thin to function as a quantum well; a pair of tunnel barriers respectively provided on the first and second surfaces of the silicon thin layer; and a first electrode and a second electrode operatively coupled to each other and formed so as to interpose the silicon thin layer and the pair of the tunnel barriers therebetween.
    Type: Grant
    Filed: August 6, 1999
    Date of Patent: August 15, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kiyoshi Morimoto, Koichiro Yuki, Yoshihiko Hirai, Kiyoyuki Morita
  • Patent number: 6081314
    Abstract: Liquid crystal display (LCD) has sub-pixel domains in each of pixels to obtain a wide viewing angle. The sub-pixel domains are formed by divided orientation alignment in which the sub-pixel domain are subjected to rubbing in different directions opposite to each other. The liquid crystal has a splay-type TN deformation structure in the first sub-pixel domain and a normal TN deformation structure in the second sub-pixel domain. The pre-tilt angles of the liquid crystal in the first domain and second domain are selected to obtain a wide viewing angle. The LCD has a shield pattern for shielding disclination causing afterimages and storage capacitor electrodes having a function as signal lines.
    Type: Grant
    Filed: June 12, 1998
    Date of Patent: June 27, 2000
    Assignee: NEC Corporation
    Inventors: Masayoshi Suzuki, Ken-Ichi Takatori, Ken Sumiyoshi, Setsuo Kaneko, Teruaki Suzuki, Hideo Shibahara, Yoshihiko Hirai
  • Patent number: 6081315
    Abstract: To provide a liquid crystal display apparatus with a wide seeing angle. The liquid crystal display apparatus of the present invention comprises a substrate with pixel electrodes, another substrate with a common electrode, and liquid crystal molecules between the substrates. Apertures are formed to divide each of the pixel electrodes into pieces for generating oblique electric fields to divide an orientation of the liquid crystal molecules. The divided pieces of the pixel electrodes are connected electrically through insulating layers at an electrode wiring portion. The control electrode for each of said pixel electrodes for controlling the orientation is placed between a boundary of the insulating layers.
    Type: Grant
    Filed: April 27, 1999
    Date of Patent: June 27, 2000
    Assignee: NEC Corporation
    Inventors: Hiroaki Matsuyama, Kazumi Kobayashi, Yoshihiko Hirai
  • Patent number: 6069675
    Abstract: In an LCD, there is used a GH-mode liquid crystal of which change in transmittivity due to variation in gap thickness is less than that of the conventional TN liquid crystal. A tablet facility is directly arranged or electrodes having the function of the tablet are formed over or below the liquid crystal. Thanks to the structure, this protection plate conventionally required to prevent the change in gap thickness resulting due to pressure of a pen input device applied to the LCD can be eliminated. Consequently, it is possible to reduce weight, volume, and parallax of the LCD. An active matrix LCD with integrated table-type input device is attainable in a simple configuration without increasing weight and volume thereof.
    Type: Grant
    Filed: October 30, 1997
    Date of Patent: May 30, 2000
    Assignee: NEC Corporation
    Inventors: Eishi Mizobata, Naoyasu Ikeda, Yoshihiko Hirai
  • Patent number: 6069678
    Abstract: A liquid crystal display device comprises shield means for shielding an electric field generated from a data line. For example, a common electrode is used as the shielding means in an IPS (In-Plane Switching) rode in which an electric field is applied in a direction respecting parallel to the substrates. Specifically, the common electrode is provided closer to the liquid crystal layer than the data line so that the common electrode covers the data line. As a result, the leak electric field from the data line is shielded by the common electrode. Therefore, the leak electric field does not adversely influence a liquid crystal layer. Consequently, the light shield area for the data line is unnecessary. This increases the aperture ratio.
    Type: Grant
    Filed: October 29, 1997
    Date of Patent: May 30, 2000
    Assignee: NEC Corporation
    Inventors: Michiaki Sakamoto, Toshiaki Ishiyama, Yoshihiko Hirai
  • Patent number: 6015978
    Abstract: The method for forming a semiconductor microstructure of this invention includes the steps of: forming a mask pattern having a first opening and a second opening on a substrate having a semiconductor layer as an upper portion thereof; and selectively etching the semiconductor layer using the mask pattern to form a semiconductor microstructure extending in a first direction parallel to a surface of the substrate, wherein, in the step of selectively etching the semiconductor layer, an etching rate in a second direction vertical to the first direction and parallel to the surface of the substrate is substantially zero with respect to an etching rate in the first direction, and a width of the semiconductor microstructure is substantially equal to a shortest distance between the first opening and the second opening in the second direction.
    Type: Grant
    Filed: October 20, 1998
    Date of Patent: January 18, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Koichiro Yuki, Kiyoyuki Morita, Kiyoshi Morimoto, Yoshihiko Hirai
  • Patent number: 5995172
    Abstract: In a tablet integrated type liquid crystal display apparatus, a first transparent substrate is provided on a view side. The first substrate is a plastic substrate having a thickness equal to or thinner than 0.6 mm, and a counter electrode is formed on the first substrate. A second substrate on which a driving layer composed of switching elements and pixel electrodes respectively connected to the switching elements is formed. The second substrate is a glass substrate having a thickness in a range of 0.6 mm to 1.1 mm. A guest host liquid crystal layer sandwiched by the first substrate and the second substrate such that the guest host liquid crystal is driven by a voltage applied between the counter electrode and the pixel electrode. A tablet electrode layer may be provided between the first substrate and the counter electrode. Alternatively, a tablet electrode layer may be provided on the first substrate on an opposite side of the counter electrode.
    Type: Grant
    Filed: January 2, 1997
    Date of Patent: November 30, 1999
    Assignee: NEC Corporation
    Inventors: Naoyasu Ikeda, Eishi Mizobata, Yoshihiko Hirai
  • Patent number: 5972744
    Abstract: A silicon island portion is formed in a quantum wire so as to be sandwiched between a pair of tunnel barrier portions of a silicon oxide film. On one side of the silicon island portion, a gate electrode for potential control is disposed with a gate insulating film of a silicon oxide film interposed therebetween. On the other side of the silicon island portion, a control electrode for potential control is disposed with an insulating film of a silicon oxide film interposed therebetween. Each of the tunnel barrier portions has a quantum wire constriction structure, which is formed by oxidizing a quantum wire, i.e., a silicon oxide film formed as a field enhanced oxide film with an atomic force microscope or the like, from its surface to a substantially center portion in its section.
    Type: Grant
    Filed: March 9, 1998
    Date of Patent: October 26, 1999
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kiyoshi Morimoto, Kiyoyuki Morita, Kiyoshi Araki, Yoshihiko Hirai, Koichiro Yuki
  • Patent number: 5945687
    Abstract: A quantization functional device includes: a silicon thin layer having a first surface and a second surface each made of a predetermined crystal surface, and the silicon thin layer being formed of single crystalline silicon having a thickness sufficiently thin to function as a quantum well; a pair of tunnel barriers respectively provided on the first and second surfaces of the silicon thin layer; and a first electrode and a second electrode operatively coupled to each other and formed so as to interpose the silicon thin layer and the pair of the tunnel barriers therebetween.
    Type: Grant
    Filed: November 27, 1996
    Date of Patent: August 31, 1999
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kiyoshi Morimoto, Koichiro Yuki, Yoshihiko Hirai, Kiyoyuki Morita
  • Patent number: 5888852
    Abstract: The method for forming a semiconductor microstructure of this invention includes the steps of: forming a mask pattern having a first opening and a second opening on a substrate having a semiconductor layer as an upper portion thereof; and selectively etching the semiconductor layer using the mask pattern to form a semiconductor microstructure extending in a first direction parallel to a surface of the substrate, wherein, in the step of selectively etching the semiconductor layer, an etching rate in a second direction vertical to the first direction and parallel to the surface of the substrate is substantially zero with respect to an etching rate in the first direction, and a width of the semiconductor microstructure is substantially equal to a shortest distance between the first opening and the second opening in the second direction.
    Type: Grant
    Filed: February 28, 1997
    Date of Patent: March 30, 1999
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Koichiro Yuki, Kiyoyuki Morita, Kiyoshi Morimoto, Yoshihiko Hirai
  • Patent number: 5781262
    Abstract: Liquid crystal display (LCD) has sub-pixel domains within each pixel to obtain a wide viewing angle. The sub-pixel domains are formed by divided orientation alignment in which the sub-pixel domain are subjected to rubbing in different directions opposite to each other. The liquid crystal has a splay-type TN deformation structure in the first sub-pixel domain and a normal TN deformation structure in the second sub-pixel domain. The pre-tilt angles of the liquid crystal in the first domain and second domain are selected to obtain a wide viewing angle. The LCD has a shield pattern for for shielding disclination causing afterimages and storage capacitor electrodes having a function as a signal lines.
    Type: Grant
    Filed: April 19, 1995
    Date of Patent: July 14, 1998
    Assignee: NEC Corporation
    Inventors: Masayoshi Suzuki, Ken-Ichi Takatori, Ken Sumiyoshi, Setsuo Kaneko, Teruaki Suzuki, Hideo Shibahara, Yoshihiko Hirai
  • Patent number: 5763545
    Abstract: A polymerization apparatus comprising a cylindrical polymerization vessel having a straight cylindrical section, a cooling means for cooling the contents of the polymerization vessel, and paddle impellers, each fixed to a central shaft positioned along the center line of the vessel and spaced apart at predetermined positions, each impeller having impeller blades for agitating the contents inside the polymerization vessel as the shaft is rotated, wherein the polymerization vessel has an inner capacity of 100 m.sup.3 or more and has a ratio L/D (the length L of the cylindrical section to the inner diameter D of the vessel) of at least 1.
    Type: Grant
    Filed: September 14, 1995
    Date of Patent: June 9, 1998
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Masatsugu Takano, Tadashi Amano, Yoshihiko Hirai, Yoshitaka Okuno
  • Patent number: 5739544
    Abstract: By etching, a first groove and a second groove are formed in a silicon substrate. Surfaces of the side walls of these grooves have a surface orientation of (111). The first and second grooves sandwich a silicon thin plate therebetween, which is formed as a part of the silicon substrate. The silicon thin plate is sufficiently thin so as to act as a quantum well. Further, a pair of silicon oxide films acting as tunneling barriers are formed on the surfaces of the side walls of the silicon thin plate, thus forming a double barrier structure. In addition, a pair of polysilicon electrodes are formed and sandwich the double barrier structure. As a result, the structure of a resonance tunneling diode, which utilizes the resonance tunneling effect, is provided. Adding a third electrode to the above structure provides a resonance tunneling transistor.
    Type: Grant
    Filed: December 12, 1995
    Date of Patent: April 14, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Koichiro Yuki, Yoshihiko Hirai, Kiyoshi Morimoto, Masaaki Niwa, Juro Yasui, Kenji Okada, Masaharu Udagawa, Kiyoyuki Morita
  • Patent number: 5618497
    Abstract: A polymerization apparatus, comprises a polymerization vessel, a reflux condenser installed outside the polymerization vessel and a pipe connected between the reflux condenser and a wall of the polymerization vessel with an end thereof opening into a gaseous phase region inside the polymerization vessel, for returning the liquid condensate to the polymerization vessel, wherein said end projects from an inner surface of the wall of the polymerization vessel into the gaseous phase region. In polymerizing a monomer having an ethylenically unsaturated double bond using the polymerization apparatus, the quantity of heat removed by the reflux condenser is increased stepwise or continuously with progress of the polymerization, such that not less than 20% of the total reaction heat generated during the whole course of the polymerization is removed by the reflux condenser. With 100 or more repeated polymerization runs, polymer scale deposition inside the vessel is minimal even below the pipe end.
    Type: Grant
    Filed: April 4, 1995
    Date of Patent: April 8, 1997
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Takuya Ueda, Yoshihiro Shirota, Yoshihiko Hirai, Toshiaki Maruyama, Tadashi Amano
  • Patent number: 5562802
    Abstract: A quantum device including a plate-like conductor part having a necking portion and a method of producing the same are disclosed.
    Type: Grant
    Filed: April 10, 1995
    Date of Patent: October 8, 1996
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kenji Okada, Kiyoshi Morimoto, Masaharu Udagawa, Koichiro Yuki, Masaaki Niwa, Yoshihiko Hirai, Juro Yasui
  • Patent number: 5543351
    Abstract: A silicon substrate comprises at least two surfaces extending substantially along respective crystal faces of (111) crystal orientation of the silicon, the crystal faces of (111) crystal orientation crossing with each other, an electrically insulating layer formed by oxidizing the silicon substrate from the surfaces, and an electrically conductive portion insulated electrically by the electrically insulating layer from an outside of the silicon substrate.
    Type: Grant
    Filed: October 31, 1994
    Date of Patent: August 6, 1996
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshihiko Hirai, Kiyoshi Morimoto, Yasuaki Terui, Masaaki Niwa, Juro Yasui, Kenji Okada, Masaharu Udagawa, Koichiro Yuki
  • Patent number: 5514614
    Abstract: By etching, a first groove and a second groove are formed in a silicon substrate. Surfaces of the side walls of these grooves have a surface orientation of (111). The first and second grooves sandwich a silicon thin plate therebetween, which is formed as a part of the silicon substrate. The silicon thin plate is sufficiently thin so as to act as a quantum well. Further, a pair of silicon oxide films acting as tunneling barriers are formed on the surfaces of the side walls of the silicon thin plate, thus forming a double barrier structure. In addition, a pair of polysilicon electrodes are formed and sandwich the double barrier structure. As a result, the structure of a resonance tunneling diode, which utilizes the resonance tunneling effect, is provided. Adding a third electrode to the above structure provides a hot electron transistor.
    Type: Grant
    Filed: April 13, 1995
    Date of Patent: May 7, 1996
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Koichiro Yuki, Yoshihiko Hirai, Koyoshi Morimoto, Masaaki Niwa, Juro Yasui, Kenji Okada, Masaharu Udagawa