Patents by Inventor Yoshihiko Yagi

Yoshihiko Yagi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10363685
    Abstract: In an ingot cutting apparatus that cuts an ingot using a plurality of stretched wires, load sensors are provided on the new wire side and the old wire side of the ingot, and loads applied to the new wire side and the old wire side of the ingot are measured using the load sensors on the new wire side and the old wire side. When measuring the loads, for example, the center of moment about the X-axis that is the running direction of the wire is calculated. When the deviation from the center of gravity of the ingot is greater than or equal to a reference value, notification for replacement of the wire, control of the conveying speed of the wire, control of the pressing speed of the ingot, and so forth are performed through a control unit.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: July 30, 2019
    Assignees: TEC GIHAN CO., LTD., PANASONIC CORPORATION
    Inventors: Masayuki Takahashi, Yoshihiko Yagi, Kazumi Koketsu, Yotaro Tsuchiya
  • Publication number: 20180085969
    Abstract: In an ingot cutting apparatus that cuts an ingot using a plurality of stretched wires, load sensors are provided on the new wire side and the old wire side of the ingot, and loads applied to the new wire side and the old wire side of the ingot are measured using the load sensors on the new wire side and the old wire side. When measuring the loads, for example, the center of moment about the X-axis that is the running direction of the wire is calculated. When the deviation from the center of gravity of the ingot is greater than or equal to a reference value, notification for replacement of the wire, control of the conveying speed of the wire, control of the pressing speed of the ingot, and so forth are performed through a control unit.
    Type: Application
    Filed: September 26, 2017
    Publication date: March 29, 2018
    Applicants: Tec Gihan Co., Ltd., Panasonic Corporation
    Inventors: Masayuki Takahashi, Yoshihiko Yagi, Kazumi Koketsu, Yotaro Tsuchiya
  • Patent number: 9438379
    Abstract: Disclosed is a communication technology in which the effect of packet loss can be easily reduced to the extent that it can be ignored, even on networks where packet loss can easily occur. Specifically, a communication device is disclosed that includes a packet loss determination unit that determines whether a packet that transmits image information has been lost, and an interpolated packet transmission unit that transmits an interpolated packet when a packet that transmits image information has been lost.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: September 6, 2016
    Assignee: Hitachi Information & Telecommunication Engineering, Ltd.
    Inventors: Asako Sakashita, Suzuka Morotomi, Takuro Kaneko, Naoya Kumada, Yukio Yasumoto, Yoshihiko Yagi
  • Patent number: 9402092
    Abstract: Task: To provide communication technology in which clock synchronization accuracy can be easily maintained, even on networks where packets can be easily lost. Resolution Means: A communication device, comprising: a transmission unit that includes a flag processing unit that, upon receipt of one or a plurality of MPEG-2 TS packets, applies flag information to the packets at a predetermined interval in the forward reproduction direction of the packets, and a time stamp application unit that generates MPEG-2 TTS packets by applying a time stamp value calculated using a GPS clock to each of the one or a plurality of MPEG-2 TS packets, including the MPEG-2 TS packets having the flag information applied by the flag processing unit, and transmits the MPEG-2 TTS packets to a transmission path.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: July 26, 2016
    Assignee: Hitachi Information & Telecommunication Engineering, Ltd.
    Inventors: Suzuka Morotomi, Takuro Kaneko, Naoya Kumada, Yukio Yasumoto, Yoshihiko Yagi
  • Publication number: 20150280864
    Abstract: Disclosed is a communication technology in which the effect of packet loss can be easily reduced to the extent that it can be ignored, even on networks where packet loss can easily occur. Specifically, a communication device is disclosed that includes a packet loss determination unit that determines whether a packet that transmits image information has been lost, and an interpolated packet transmission unit that transmits an interpolated packet when a packet that transmits image information has been lost.
    Type: Application
    Filed: July 30, 2014
    Publication date: October 1, 2015
    Inventors: Asako SAKASHITA, Suzuka MOROTOMI, Takuro KANEKO, Naoya KUMADA, Yukio YASUMOTO, Yoshihiko YAGI
  • Publication number: 20150156524
    Abstract: Task: To provide communication technology in which clock synchronization accuracy can be easily maintained, even on networks where packets can be easily lost. Resolution Means: A communication device, comprising: a transmission unit that includes a flag processing unit that, upon receipt of one or a plurality of MPEG-2 TS packets, applies flag information to the packets at a predetermined interval in the forward reproduction direction of the packets, and a time stamp application unit that generates MPEG-2 TTS packets by applying a time stamp value calculated using a GPS clock to each of the one or a plurality of MPEG-2 TS packets, including the MPEG-2 TS packets having the flag information applied by the flag processing unit, and transmits the MPEG-2 TTS packets to a transmission path.
    Type: Application
    Filed: June 27, 2014
    Publication date: June 4, 2015
    Inventors: Suzuka MOROTOMI, Takuro KANEKO, Naoya KUMADA, Yukio YASUMOTO, Yoshihiko YAGI
  • Patent number: 8809693
    Abstract: A three-dimensional circuit board is formed by comprising a board, a first wiring-electrode group provided on a plurality of steps above the board, and a second wiring-electrode connected to the first wiring-electrode group at least in an altitude direction, in which at least a connecting portion between the first wiring-electrode group and the second wiring-electrode is integrated in a continuously identical shape.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: August 19, 2014
    Assignee: Panasonic Corporation
    Inventors: Daisuke Sakurai, Yoshihiko Yagi
  • Patent number: 8575751
    Abstract: A conductive bump formed on an electrode surface of an electronic component. This conductive bump is composed of a plurality of photosensitive resin layers having different conductive filler contents. Consequently, this conductive bump is able to realize conflicting functions, namely, improvement in adhesion strength with the electrode and reduction of contact resistance.
    Type: Grant
    Filed: March 4, 2008
    Date of Patent: November 5, 2013
    Assignee: Panasonic Corporation
    Inventors: Daisuke Sakurai, Yoshihiko Yagi
  • Patent number: 8208270
    Abstract: Three-dimensional structure (40) of the present invention includes first module board (28), second module board (37), and substrate joining member (10) that unifies board (28) and board (37) into one body, thereby electrically connecting these two elements together. The unification is done by molding the outer wall of housing (12) of substrate joining member (10) with resin (29). Substrate joining member (10) used in the three-dimensional structure (40) includes multiple lead terminals (14) made of conductive material, and a frame-shaped and insulating housing (12) to which frame the lead terminals (14) are fixed vertically in a predetermined array. Housing (12) includes projections (18) on at least two outer wall faces of its frame shape.
    Type: Grant
    Filed: April 23, 2007
    Date of Patent: June 26, 2012
    Assignee: Panasonic Corporation
    Inventors: Masato Mori, Daido Komyoji, Koichi Nagai, Yoshihiko Yagi
  • Publication number: 20120125676
    Abstract: A three-dimensional circuit board is formed by comprising a board, a first wiring-electrode group provided on a plurality of steps above the board, and a second wiring-electrode connected to the first wiring-electrode group at least in an altitude direction, in which at least a connecting portion between the first wiring-electrode group and the second wiring-electrode is integrated in a continuously identical shape.
    Type: Application
    Filed: January 31, 2012
    Publication date: May 24, 2012
    Applicant: Panasonic Corporation
    Inventors: Daisuke Sakurai, Yoshihiko Yagi
  • Patent number: 8159829
    Abstract: Relay substrate (1) connecting between at least a first circuit board and a second circuit board, including housing (10) having recess (10a) provided in the outer circumference and hole (22) provided in the inner circumference; plural connecting terminal electrodes (12a, 12c) connecting between the top and bottom surfaces of housing (10); shield electrode (11) provided in recess (10a); and ground electrode (13) provided on a part of the top and bottom surfaces of housing (10).
    Type: Grant
    Filed: March 23, 2007
    Date of Patent: April 17, 2012
    Assignee: Panasonic Corporation
    Inventors: Masato Mori, Daido Komyoji, Koichi Nagai, Yoshihiko Yagi
  • Patent number: 8134081
    Abstract: A three-dimensional circuit board is formed by comprising a board, a first wiring-electrode group provided on a plurality of steps above the board, and a second wiring-electrode connected to the first wiring-electrode group at least in an altitude direction, in which at least a connecting portion between the first wiring-electrode group and the second wiring-electrode is integrated in a continuously identical shape.
    Type: Grant
    Filed: January 12, 2007
    Date of Patent: March 13, 2012
    Assignee: Panasonic Corporation
    Inventors: Daisuke Sakurai, Yoshihiko Yagi
  • Patent number: 8120188
    Abstract: An electronic component mounting structure includes an electronic component provided with a plurality of electrode terminals, and a mounting substrate provided with connector terminals in positions corresponding to the electrode terminals. An electrode terminal is connected to a connector terminal via a protrusion electrode disposed on the electrode terminal or the connector terminal, and the protrusion electrode includes a conductive filler and a photosensitive resin. The photosensitive resin varies in resin component crosslink density in the height direction of the protrusion electrode.
    Type: Grant
    Filed: November 20, 2007
    Date of Patent: February 21, 2012
    Assignee: Panasonic Corporation
    Inventors: Daisuke Sakurai, Yoshihiko Yagi
  • Patent number: 8119449
    Abstract: An electronic part mounting structure includes electronic part having a plurality of electrode terminals, a substrate provided with connection terminals in locations corresponding to these electrode terminals, and protruding electrode for connecting one of electrode terminals and one of connection terminals, where electrode terminal of electronic part and connection terminal of substrate are connected through protruding electrode and protruding electrode is formed of a conductive resin including a photosensitive resin and a conductive filler.
    Type: Grant
    Filed: March 6, 2007
    Date of Patent: February 21, 2012
    Assignee: Panasonic Corporation
    Inventors: Daisuke Sakurai, Yoshihiko Yagi
  • Patent number: 8033016
    Abstract: A protruding electrodes is formed on a lead electrode of an electronic component, and the protruding electrodes comprises a first conductor formed on the lead electrode of the electronic component, and a second conductor overlaid on the first conductor by using a transfer mold having a concavity. By virtue of this structure, protruding electrodes of any configuration can be formed in fine pitches.
    Type: Grant
    Filed: April 14, 2006
    Date of Patent: October 11, 2011
    Assignee: Panasonic Corporation
    Inventors: Kunio Hibino, Yoshihiro Tomura, Yoshihiko Yagi, Kazuhiro Nishikawa
  • Patent number: 8018731
    Abstract: Interconnect substrate (1) that connects at least the first circuit board and the second circuit board. Interconnect substrate (1) includes housing (1) and connecting terminal electrodes for connecting the top and bottom faces of housing (10). Housing (10) has protrusion (11) on its outer periphery and opening (13) in its inner periphery.
    Type: Grant
    Filed: June 19, 2007
    Date of Patent: September 13, 2011
    Assignee: Panasonic Corporation
    Inventors: Daisuke Sakurai, Masato Mori, Yoshihiko Yagi
  • Patent number: 7928566
    Abstract: Conductive bump (17) formed on a surface of electrode terminal (11) of an electronic component. Conductive bump (17) is composed of at least a plurality of cured resin materials having different conductive filler densities. Thus, a short circuit and a connection failure due to crush of conductive bump (17) at the time of mounting can be prevented.
    Type: Grant
    Filed: November 20, 2007
    Date of Patent: April 19, 2011
    Assignee: Panasonic Corporation
    Inventors: Yoshihiko Yagi, Daisuke Sakurai
  • Patent number: 7845954
    Abstract: A first circuit board (1) mounted with an electronic component (16) and a second circuit board (2) are vertically connected three-dimensionally through an interconnecting board (3) wherein the terminal portion (6) of the land electrode (5) on the interconnecting board (3) is buried in the termination material (9) of the interconnecting board (3). Consequently, the chance of peeling or cracking due to peeling stress or shearing stress acting between the upper/lower circuit boards and the land electrode by high density mounting, thermal shock or falling impact can be suppressed or buffered resulting in high reliability.
    Type: Grant
    Filed: April 17, 2006
    Date of Patent: December 7, 2010
    Assignee: Panasonic Corporation
    Inventors: Yoshihiro Tomura, Yasushi Nakagiri, Kunio Hibino, Yoshihiko Yagi, Akihiro Miyashita, Masahiro Ono, Masato Mori
  • Patent number: 7762819
    Abstract: A substrate connecting member connects two circuit boards connected together while maintaining high reliability of the junctions between itself and the circuit boards even if the circuit boards are warped by temperature change of an impact load. The substrate connecting member includes a frame member made of an insulating resin; slit grooves formed in at least one of the inner and outer surfaces of frame side portions composing the frame member, the slit grooves being formed throughout the entire length of the frame side portions in the direction perpendicular to the thickness direction of the frame side portions; and connection conductor portions having connection terminals provided on the top and bottom surfaces, respectively, of the frame side portions in the thickness direction and connecting conductors each connecting connection terminals.
    Type: Grant
    Filed: July 6, 2006
    Date of Patent: July 27, 2010
    Assignee: Panasonic Corporation
    Inventors: Masato Mori, Yoshihiko Yagi, Masahiro Ono, Yoshihiro Tomura, Kunio Hibino, Yasushi Nakagiri, Akihiro Miyashita, Kunio Sakurai
  • Publication number: 20100052189
    Abstract: Electronic component mounting structure (1) comprising electronic component (10) provided with a plurality of electrode terminals (10a), mounting substrate (12) provided with connector terminals (12a) in positions corresponding to electrode terminals (10a), wherein electrode terminal (10a) is connected to connector terminal (12a) via protrusion electrode (13) disposed on electrode terminal (10a) or connector terminal (12a), and protrusion electrode (13) includes at least conductive filler (13a) and photosensitive resin (13b), and varies in resin component crosslink density of photosensitive resin (13b) in the height direction of protrusion electrode (13).
    Type: Application
    Filed: November 20, 2007
    Publication date: March 4, 2010
    Inventors: Daisuke Sakurai, Yoshihiko Yagi