Patents by Inventor Yoshihiko Yasu
Yoshihiko Yasu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10896919Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.Type: GrantFiled: September 10, 2019Date of Patent: January 19, 2021Assignee: Renesas Electronics CorporationInventors: Yusuke Kanno, Hiroyuki Mizuno, Yoshihiko Yasu, Kenji Hirose, Takahiro Irita
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Patent number: 10751924Abstract: A method for making an activatable material having a handling film layer thereon, comprising the steps of providing a continuous mass of a polymeric material having a longitudinal axis and being capable of adhering to a metal surface; applying a handling layer (e.g., film) over at least one side of the mass; forming stress relief indentations in the mass, with the handling layer at least partially extending into the indentations, wherein the stress relief indentations allow a resulting part to be applied in conforming geometry with a surface to which it is applied. The teachings also contemplate parts made by the above method and use thereof to bond to surfaces having a non-planar portion.Type: GrantFiled: June 1, 2017Date of Patent: August 25, 2020Assignee: ZEPHYROS, INC.Inventors: David G. Billette, Dean W. Smitterberg, Yoshihiko Yasu
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Publication number: 20200006384Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.Type: ApplicationFiled: September 10, 2019Publication date: January 2, 2020Inventors: Yusuke KANNO, Hiroyuki MIZUNO, Yoshihiko YASU, Kenji HIROSE, Takahiro IRITA
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Patent number: 10446581Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.Type: GrantFiled: June 6, 2018Date of Patent: October 15, 2019Assignee: Renesas Electronics CorporationInventors: Yusuke Kanno, Hiroyuki Mizuno, Yoshihiko Yasu, Kenji Hirose, Takahiro Irita
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Patent number: 10317981Abstract: A data processing device includes a load circuit including a central processing unit and operated by supplied electric power, a step-down power supply circuit stepping down an external power supply voltage and including an output node coupled to the load circuit, the step-down power supply circuit including a first step-down unit stepping down the external power supply voltage, and a bias current control circuit controlling a magnitude of bias current flowing through an auxiliary path from the output node to a ground, the auxiliary path is separate from a path to the load circuit, and a control circuit increasing the magnitude of the bias current, prior to a change of an operation state of the load circuit by which a relatively large change occurs to an amount of current consumed by the load circuit.Type: GrantFiled: December 6, 2016Date of Patent: June 11, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Soichi Kobayashi, Akira Oizumi, Yoshihiko Yasu, Hiromi Notani
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Publication number: 20180286885Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.Type: ApplicationFiled: June 6, 2018Publication date: October 4, 2018Inventors: Yusuke KANNO, Hiroyuki MIZUNO, Yoshihiko YASU, Kenji HIROSE, Takahiro IRITA
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Patent number: 10014320Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.Type: GrantFiled: August 25, 2016Date of Patent: July 3, 2018Assignee: Renesas Electronics CorporationInventors: Yusuke Kanno, Hiroyuki Mizuno, Yoshihiko Yasu, Kenji Hirose, Takahiro Irita
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Publication number: 20170297246Abstract: A method for making an activatable material having a handling film layer thereon, comprising the steps of providing a continuous mass of a polymeric material having a longitudinal axis and being capable of adhering to a metal surface; applying a handling layer (e.g., film) over at least one side of the mass; forming stress relief indentations in the mass, with the handling layer at least partially extending into the indentations, wherein the stress relief indentations allow a resulting part to be applied in conforming geometry with a surface to which it is applied. The teachings also contemplate parts made by the above method and use thereof to bond to surfaces having a non-planar portion.Type: ApplicationFiled: June 1, 2017Publication date: October 19, 2017Inventors: David G. Billette, Dean W. Smitterberg, Yoshihiko Yasu
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Patent number: 9701093Abstract: A method for making an activatable material having a handling film layer thereon, comprising the steps of providing a continuous mass of a polymeric material having a longitudinal axis and being capable of adhering to a metal surface; applying a handling layer (e.g., film) over at least one side of the mass; forming stress relief indentations in the mass, with the handling layer at least partially extending into the indentations, wherein the stress relief indentations allow a resulting part to be applied in conforming geometry with a surface to which it is applied. The teachings also contemplate parts made by the above method and use thereof to bond to surfaces having a non-planar portion.Type: GrantFiled: June 24, 2013Date of Patent: July 11, 2017Assignee: ZEPHYROS, INC.Inventors: David G. Billette, Dean W. Smitterberg, Yoshihiko Yasu
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Publication number: 20170083080Abstract: A data processing device includes a load circuit including a central processing unit and operated by supplied electric power, a step-down power supply circuit stepping down an external power supply voltage and including an output node coupled to the load circuit, the step-down power supply circuit including a first step-down unit stepping down the external power supply voltage, and a bias current control circuit controlling a magnitude of bias current flowing through an auxiliary path from the output node to a ground, the auxiliary path is separate from a path to the load circuit, and a control circuit increasing the magnitude of the bias current, prior to a change of an operation state of the load circuit by which a relatively large change occurs to an amount of current consumed by the load circuit.Type: ApplicationFiled: December 6, 2016Publication date: March 23, 2017Inventors: Soichi Kobayashi, Akira Oizumi, Yoshihiko Yasu, Hiromi Notani
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Patent number: 9529402Abstract: A step down unit steps down an external power supply voltage Vcc. A bias current control circuit controls the magnitude of bias current flowing through an auxiliary path connecting an output node and the ground. A system controller increases the magnitude of the bias current, prior to a change of the operation state of a load circuit by which a relatively large change occurs to the amount of current consumed by the load circuit including a central processing unit.Type: GrantFiled: September 2, 2010Date of Patent: December 27, 2016Assignee: Renesas Electronics CorporationInventors: Soichi Kobayashi, Akira Oizumi, Yoshihiko Yasu, Hiromi Notani
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Publication number: 20160365358Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.Type: ApplicationFiled: August 25, 2016Publication date: December 15, 2016Inventors: Yusuke KANNO, Hiroyuki MIZUNO, Yoshihiko YASU, Kenji HIROSE, Takahiro IRITA
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Patent number: 9455699Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.Type: GrantFiled: June 23, 2015Date of Patent: September 27, 2016Assignee: Renesas Electronics CorporationInventors: Yusuke Kanno, Hiroyuki Mizuno, Yoshihiko Yasu, Kenji Hirose, Takahiro Irita
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Publication number: 20150295572Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.Type: ApplicationFiled: June 23, 2015Publication date: October 15, 2015Inventors: Yusuke KANNO, Hiroyuki MIZUNO, Yoshihiko YASU, Kenji HIROSE, Takahiro IRITA
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Patent number: 9087818Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.Type: GrantFiled: February 21, 2014Date of Patent: July 21, 2015Assignee: Renesas Electronics CorporationInventors: Yusuke Kanno, Hiroyuki Mizuno, Yoshihiko Yasu, Kenji Hirose, Takahiro Irita
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Publication number: 20140322493Abstract: A method for making an activatable material having a handling film layer thereon, comprising the steps of providing a continuous mass of a polymeric material having a longitudinal axis and being capable of adhering to a metal surface; applying a handling layer (e.g., film) over at least one side of the mass; forming stress relief indentations in the mass, with the handling layer at least partially extending into the indentations, wherein the stress relief indentations allow a resulting part to be applied in conforming geometry with a surface to which it is applied. The teachings also contemplate parts made by the above method and use thereof to bond to surfaces having a non-planar portion.Type: ApplicationFiled: June 24, 2013Publication date: October 30, 2014Inventors: David G. Billette, Dean W. Smitterberg, Yoshihiko Yasu
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Patent number: 8829968Abstract: A semiconductor integrated circuit device provided with a first circuit block BLK1, a second circuit block DRV1 and a conversion circuit MIO1 for connecting the first circuit block to the second circuit block. The first circuit block includes a first mode for applying a supply voltage and a second mode for shutting off the supply voltage. The conversion circuit is provided with a function for maintaining the potential of an input node of the second circuit block at an operation potential, thereby suppressing a penetrating current flow when the first circuit block is in the second mode. The conversion circuit (MIO1 to MIO4) are commonly used for connecting circuit blocks.Type: GrantFiled: September 8, 2009Date of Patent: September 9, 2014Assignee: Renesas Electronics CorporationInventors: Hiroyuki Mizuno, Yusuke Kanno, Kazumasa Yanagisawa, Yoshihiko Yasu, Nobuhiro Oodaira
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Publication number: 20140167819Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.Type: ApplicationFiled: February 21, 2014Publication date: June 19, 2014Applicant: Renesas Electronics CorporationInventors: Yusuke KANNO, Hiroyuki MIZUNO, Yoshihiko YASU, Kenji HIROSE, Takahiro IRITA
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Patent number: 8730703Abstract: Efficient reduction in power consumption is achieved by combinational implementation of a power cutoff circuit technique using power supply switch control and a DVFS technique for low power consumption. A power supply switch section fed with power supply voltage, a circuit block in which a power cutoff is performed by the power supply switch section, and a level shifter are formed in a DEEP-NWELL region formed over a semiconductor substrate. Another power supply switch section fed with another power supply voltage, a circuit block in which a power cutoff is performed by the power supply switch section, and a level shifter are formed in another DEEP-NWELL region formed over the semiconductor substrate. In this arrangement, there arises no possibility of short-circuiting between different power supplies via each DEEP-NWELL region formed over the semiconductor substrate.Type: GrantFiled: January 24, 2013Date of Patent: May 20, 2014Assignee: Renesas Electronics CorporationInventors: Kazuki Fukuoka, Yasuto Igarashi, Ryo Mori, Yoshihiko Yasu, Toshio Sasaki
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Patent number: 8683414Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.Type: GrantFiled: April 18, 2013Date of Patent: March 25, 2014Assignee: Renesas Electronics CorporationInventors: Yusuke Kanno, Hiroyuki Mizuno, Yoshihiko Yasu, Kenji Hirose, Takahiro Irita