Patents by Inventor Yoshihiro Hayashi

Yoshihiro Hayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180340765
    Abstract: To provide a wireless communication module that implements the function to detect a human body in a conserved space and is capable of detecting a proximity to human bodies with high accuracy. A wireless communication module includes an antenna unit and a proximity detector which detects that a human body has approached the module. The antenna unit includes an antenna and a first filter which is comprised of distributed constant elements. The proximity detector for human bodies uses the antenna and the first filter as an electrode to detect capacitance.
    Type: Application
    Filed: April 17, 2018
    Publication date: November 29, 2018
    Inventors: Tatsuya SERIZAWA, Yoshihiro HAYASHI, Noriaki MATSUNO
  • Patent number: 10115772
    Abstract: A semiconductor device has a resistance change element that is high in the holding resistance of a low resistance (On) state while securing a memory window. In a resistance random access memory including selection transistors and resistance change elements coupled in series to the selection transistors, the resistance change element uses a lower electrode that applies a positive voltage when being transited to a high resistance (Off) state, an upper electrode that faces the lower electrode, and a resistance change layer that is sandwiched between the lower electrode and the upper electrode and that uses an oxide of transition metal. The resistance change layer contains nitrogen. The concentration of nitrogen on the lower electrode side is higher than that on the upper electrode side. The nitrogen in the resistance change layer exhibits a concentration gradient continuously declined from the lower electrode side to the upper electrode side.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: October 30, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Makoto Ueki, Koji Masuzaki, Takashi Hase, Yoshihiro Hayashi
  • Publication number: 20180175136
    Abstract: An inductor element is formed in a multiple layer lead structure including a lead, an insulative layer that insulates leads above and below, and a via provided in the insulative layer and connecting leads above and below wherein lead layers are multiply laminated layers, characterized in that: at least a portion of at least a pair of vertically adjacent leads are coiled leads; the coiled leads are connected in series, wherein current directions of vertically adjacent coiled leads are the same by a via provided on an end portion thereof, and form a serial inductance; and an inter-lead capacitance of the vertically adjacent coiled leads is larger than an inter-lead capacitance between other coiled leads formed in the same lead layer.
    Type: Application
    Filed: February 5, 2018
    Publication date: June 21, 2018
    Applicant: Renesas Electronics Corporation
    Inventors: Kenichiro HIJIOKA, Akira TANABE, Yoshihiro HAYASHI
  • Publication number: 20180152829
    Abstract: A wireless communication apparatus includes a communication controller and an identification information setup portion. The communication controller establishes first communication, namely, communication with a first wireless communication apparatus having identification information already set and receives first information, namely, information to settle the identification information to be set, from the first wireless communication apparatus. The identification information setup portion sets the identification information for the wireless communication apparatus based on the first information.
    Type: Application
    Filed: September 28, 2017
    Publication date: May 31, 2018
    Inventors: Taku FUJIWARA, Yoshihiro HAYASHI
  • Patent number: 9923045
    Abstract: An inductor element is formed in a multiple layer lead structure including a lead, an insulative layer that insulates leads above and below, and a via provided in the insulative layer and connecting leads above and below wherein lead layers are multiply laminated layers, characterized in that: at least a portion of at least a pair of vertically adjacent leads are coiled leads; the coiled leads are connected in series, wherein current directions of vertically adjacent coiled leads are the same by a via provided on an end portion thereof, and form a serial inductance; and an inter-lead capacitance of the vertically adjacent coiled leads is larger than an inter-lead capacitance between other coiled leads formed in the same lead layer.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: March 20, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Kenichiro Hijioka, Akira Tanabe, Yoshihiro Hayashi
  • Publication number: 20180064319
    Abstract: An electronic endoscope system including a light source unit alternately repeats irradiation and non-irradiation of illumination light while alternately switching illumination light to be irradiated between first and second illumination lights which is different from at least one of a light amount and a spectral property from the first illumination light; an image pickup device that captures a subject illuminated with the illumination light; and an image pickup device control that reads, during a non-irradiation period of the illumination light following an irradiation period of the illumination light, charges which have been accumulated in the image pickup device during the irradiation period, and wherein the irradiation period of the first illumination light and the second illumination light are set to have different lengths depending on at least one of a difference in light amount and a difference in spectral property between the first illumination light and the second illumination light.
    Type: Application
    Filed: April 22, 2016
    Publication date: March 8, 2018
    Applicant: HOYA CORPORATION
    Inventor: Yoshihiro HAYASHI
  • Publication number: 20180032019
    Abstract: An image forming apparatus includes an image forming section that forms an image on a continuous medium, a transport unit that transports the continuous medium, and a detection unit that detects breakage of the continuous medium transported by the transport unit from a transport state of the continuous medium.
    Type: Application
    Filed: April 26, 2017
    Publication date: February 1, 2018
    Applicant: FUJI XEROX CO., LTD.
    Inventors: Yoshihiro HAYASHI, Yuki YOKOYAMA
  • Patent number: 9798274
    Abstract: A preheating device includes a heating member that is capable of heating a continuous medium, and a movement unit that moves at least one of the continuous medium and the heating member in a direction in which the continuous medium and the heating member move relatively closer to each other or in a direction in which the continuous medium and the heating member move relatively away from each other. The movement unit moves at least one of the continuous medium and the heating member in the direction in which the continuous medium and the heating member move relatively closer to each other if predetermined heating conditions are satisfied, and the movement unit moves at least one of the continuous medium and the heating member in the direction in which the continuous medium and the heating member move relatively away from each other if the heating conditions are not satisfied.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: October 24, 2017
    Assignee: FUJI XEROX CO., LTD.
    Inventors: Yoshihiro Hayashi, Mizuki Sugino, Toshinori Sasaki, Koichi Kimura, Mitsutoshi Hongo
  • Publication number: 20170255137
    Abstract: A preheating device includes a heating member that is capable of heating a continuous medium, and a movement unit that moves at least one of the continuous medium and the heating member in a direction in which the continuous medium and the heating member move relatively closer to each other or in a direction in which the continuous medium and the heating member move relatively away from each other. The movement unit moves at least one of the continuous medium and the heating member in the direction in which the continuous medium and the heating member move relatively closer to each other if predetermined heating conditions are satisfied, and the movement unit moves at least one of the continuous medium and the heating member in the direction in which the continuous medium and the heating member move relatively away from each other if the heating conditions are not satisfied.
    Type: Application
    Filed: August 4, 2016
    Publication date: September 7, 2017
    Applicant: FUJI XEROX Co., Ltd.
    Inventors: Yoshihiro HAYASHI, Mizuki SUGINO, Toshinori SASAKI, Koichi KIMURA, Mitsutoshi HONGO
  • Patent number: 9754816
    Abstract: The method of manufacturing a semiconductor device, including preparing a semiconductor substrate, forming a first insulating layer over said semiconductor substrate, forming first grooves in the first insulating film, forming a gate electrode and a first interconnect in the first grooves, respectively, forming a gate insulating film over the gate electrode, forming a semiconductor layer over the gate insulating, forming a second insulating layer over the semiconductor layer and the first insulating film, forming a via in the second insulating layer, and forming a second interconnect such that the second interconnect is connected to the semiconductor layer through the via. The gate electrode, the first interconnect and the second interconnect are formed by Cu or Cu alloy, respectively.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: September 5, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshihiro Hayashi, Naoya Inoue, Kishou Kaneko
  • Patent number: 9679647
    Abstract: Included are memory cells each including a resistance change element and a control circuit. The circuit performs an On writing process for applying, to the memory cell, an On writing pulse for the cell to be in a resistance state where a resistance value of the resistance change element is lower than a first reference value and an Off writing process for applying an Off writing pulse with an opposite polarity to the On writing pulse for a high resistance state with a second reference value or greater. The circuit applies, in the On writing process, a trial pulse having the same polarity as that of the On writing pulse and having the pulse width shorter than that of the On writing pulse and a reset pulse having the same polarity as that of the On writing pulse, in this order before applying the On writing pulse to the cell.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: June 13, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Makoto Ueki, Koji Masuzaki, Masaharu Matsudaira, Takashi Hase, Yoshihiro Hayashi
  • Patent number: 9680031
    Abstract: Provided is an in-wiring-layer active element (component) which allows for electrical isolation between a gate electrode and a channel in a top gate structure. A semiconductor device includes a first wiring layer, a second wiring layer, and a semiconductor element. The first wiring layer has a first interlayer insulating layer, and a first wire embedded in the first interlayer insulating layer. The second wiring layer has a second interlayer insulating layer, and second wires embedded in the second interlayer insulating layer. The semiconductor element is provided at least in the second wiring layer. The semiconductor element includes a semiconductor layer provided in the second wiring layer, a gate insulating film provided in contact with the semiconductor layer, a gate electrode provided on the opposite side of the semiconductor layer via the first gate insulating film, and a first side wall film provided over a side surface of the semiconductor layer.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: June 13, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroshi Sunamura, Kishou Kaneko, Yoshihiro Hayashi
  • Publication number: 20170133434
    Abstract: A semiconductor device has a resistance change element that is high in the holding resistance of a low resistance (On) state while securing a memory window. In a resistance random access memory including selection transistors and resistance change elements coupled in series to the selection transistors, the resistance change element uses a lower electrode that applies a positive voltage when being transited to a high resistance (Off) state, an upper electrode that faces the lower electrode, and a resistance change layer that is sandwiched between the lower electrode and the upper electrode and that uses an oxide of transition metal. The resistance change layer contains nitrogen. The concentration of nitrogen on the lower electrode side is higher than that on the upper electrode side. The nitrogen in the resistance change layer exhibits a concentration gradient continuously declined from the lower electrode side to the upper electrode side.
    Type: Application
    Filed: October 26, 2016
    Publication date: May 11, 2017
    Inventors: Makoto UEKI, Koji MASUZAKI, Takashi HASE, Yoshihiro HAYASHI
  • Patent number: 9558824
    Abstract: To improve information retention resistance of a resistance change memory which requires high information retention resistance. On the assumption that a special data storage memory and a general-purpose data storage memory are distinguished from each other, a forming operation small in resistance rise rate is used for an information writing operation of the special data storage memory. A switching operation is used for information writing of the general-purpose data storage memory. That is, the special data storage memory is configured so as to store information while adapting an initial resistance state to “0” whereas adapting a low resistance state to “1”. On the other hand, the general-purpose data storage memory is configured so as to store information while adapting a high resistance state to “0” whereas adapting a low resistance state to “1”.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: January 31, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Makoto Ueki, Takashi Hase, Yoshihiro Hayashi
  • Publication number: 20170000393
    Abstract: A light source device is configured to have a light source configured to emit white light, a rotatable turret provided with multiple kinds of predetermined light passing areas respectively extract light components having different wavelength ranges from the white light incident from the light source, the multiple kinds of predetermined light passing areas being arranged in a circumferential direction of the rotatable turret, and white light passing areas each allowing the white light to pass therethrough being arranged in the circumferential direction of the rotatable turret and between the predetermined wavelength light passing areas, and a driving means configured rotate the rotatable turret so that the multiple kinds of predetermined wavelength light passing areas and the white light passing areas are alternately inserted into a light path of the white light one by one at a timing which is synchronized with a predetermined photographing period.
    Type: Application
    Filed: February 8, 2016
    Publication date: January 5, 2017
    Applicant: HOYA CORPORATION
    Inventors: Yoshihiro HAYASHI, Yuuki IKEDA, Yuya MASUKAWA
  • Patent number: 9530769
    Abstract: A semiconductor device includes a semiconductor substrate on which a semiconductor device is formed; first and second pads; a first insulating film which is formed above the semiconductor substrate; a plurality of wiring lines which are embedded in ditches provided in the first insulating film; a second insulating film provided to cover the first insulating film and the plurality of wiring lines; a semiconductor layer formed on the second insulating film; a source electrode connected with the semiconductor layer; and a drain electrode connected with the semiconductor layer. The plurality of wiring lines includes a gate electrode provided in a position which is opposite to the semiconductor layer. The semiconductor layer, the source electrode, the drain electrode and the gate electrode configure an ESD protection device to discharge a current by ESD surge from the first pad to the second pad.
    Type: Grant
    Filed: January 14, 2016
    Date of Patent: December 27, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Kishou Kaneko, Naoya Inoue, Yoshihiro Hayashi
  • Publication number: 20160365144
    Abstract: Included are memory cells each including a resistance change element and a control circuit. The circuit performs an On writing process for applying, to the memory cell, an On writing pulse for the cell to be in a resistance state where a resistance value of the resistance change element is lower than a first reference value and an Off writing process for applying an Off writing pulse with an opposite polarity to the On writing pulse for a high resistance state with a second reference value or greater. The circuit applies, in the On writing process, a trial pulse having the same polarity as that of the On writing pulse and having the pulse width shorter than that of the On writing pulse and a reset pulse having the same polarity as that of the On writing pulse, in this order before applying the On writing pulse to the cell.
    Type: Application
    Filed: April 15, 2016
    Publication date: December 15, 2016
    Inventors: Makoto UEKI, Koji MASUZAKI, Masaharu MATSUDAIRA, Takashi HASE, Yoshihiro HAYASHI
  • Patent number: 9501015
    Abstract: An image forming apparatus includes an image forming unit, a heating unit, and a fixing unit. The image forming unit uses a toner including a flat pigment. The heating unit heats a recording medium. The fixing unit allows the recording medium to pass therethrough so as to cause an image formed on the recording medium to be fixed onto the recording medium by heat. In the image forming apparatus, the heating unit heats the recording medium on which the image has not been formed, the image forming unit forms the image on the recording medium having been heated, and the fixing unit fixes the image having been formed onto the recording medium.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: November 22, 2016
    Assignee: FUJI XEROX CO., LTD.
    Inventors: Aya Kakishima, Miho Ikeda, Koichiro Yuasa, Yasumitsu Harashima, Toko Hara, Yoshihiro Hayashi
  • Patent number: 9496403
    Abstract: A circuit including an inverter is provided for a wiring layer. A semiconductor device is provided with a wiring layer circuit which is formed over an insulating film and includes at least one inverter element. The inverter is provided with a first transistor element and a resistance element which is connected to the first transistor via a connection node. The first transistor element is provided with a gate electrode which is embedded in an interlayer insulating film including the insulating film, a gate insulating film which is formed over the interlayer insulating film and the gate electrode, and a first semiconductor layer which is formed over the gate insulating film between a source electrode and a drain electrode. The resistance element is provided with a second semiconductor layer which functions as a resistance. The first semiconductor layer and the second semiconductor layer are formed in the same layer.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: November 15, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kishou Kaneko, Hiroshi Sunamura, Yoshihiro Hayashi
  • Publication number: 20160284405
    Abstract: To improve information retention resistance of a resistance change memory which requires high information retention resistance. On the assumption that a special data storage memory and a general-purpose data storage memory are distinguished from each other, a forming operation small in resistance rise rate is used for an information writing operation of the special data storage memory. A switching operation is used for information writing of the general-purpose data storage memory. That is, the special data storage memory is configured so as to store information while adapting an initial resistance state to “0” whereas adapting a low resistance state to “1”. On the other hand, the general-purpose data storage memory is configured so as to store information while adapting a high resistance state to “0” whereas adapting a low resistance state to “1”.
    Type: Application
    Filed: January 11, 2016
    Publication date: September 29, 2016
    Inventors: Makoto Ueki, Takashi Hase, Yoshihiro Hayashi