Patents by Inventor Yoshihiro Irokawa

Yoshihiro Irokawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9190483
    Abstract: An AlN single crystal Schottky barrier diode including: an AlN single crystal substrate having a defect density of 106 cm?2 or less and a thickness of 300 ?m or more; a first electrode formed on one surface of the AlN single crystal substrate; and a second electrode formed on one surface of the AlN single crystal substrate while being spaced apart from the first electrode, the AlN single crystal Schottky barrier diode being provided with: a rectifying property such that an on-off ratio at the time of applying 10 V and ?40 V is at least 103 even at a high temperature of 573 K; a high voltage resistance such that a voltage can be applied at least within a range of ?40 V to 10 V; and a low on-resistance characteristic such that a current begins to flow at no greater than 5 V.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: November 17, 2015
    Assignee: NATIONAL INSTITUTE FOR MATERIALS SCIENCE
    Inventors: Yoshihiro Irokawa, Kiyoshi Shimamura, Encarnacion Antonia Garcia Villora
  • Patent number: 9159800
    Abstract: An AlN single crystal Schottky barrier diode including: an AlN single crystal substrate having a defect density of 106 cm?2 or less and a thickness of 300 ?m or more; a first electrode formed on one surface of the AlN single crystal substrate; and a second electrode formed on one surface of the AlN single crystal substrate while being spaced apart from the first electrode, the AlN single crystal Schottky barrier diode being provided with: a rectifying property such that an on-off ratio at the time of applying 10 V and ?40 V is at least 103 even at a high temperature of 573 K; a high voltage resistance such that a voltage can be applied at least within a range of ?40 V to 10 V; and a low on-resistance characteristic such that a current begins to flow at no greater than 5 V.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: October 13, 2015
    Assignee: NATIONAL INSTITUTE FOR MATERIALS SCIENCE
    Inventors: Yoshihiro Irokawa, Kiyoshi Shimamura, Encarnacion Antonia Garcia Villora
  • Publication number: 20150034961
    Abstract: An AlN single crystal Schottky barrier diode including: an AlN single crystal substrate having a defect density of 106 cm?2 or less and a thickness of 300 ?m or more; a first electrode formed on one surface of the AlN single crystal substrate; and a second electrode formed on one surface of the AlN single crystal substrate while being spaced apart from the first electrode, the AlN single crystal Schottky barrier diode being provided with: a rectifying property such that an on-off ratio at the time of applying 10 V and ?40 V is at least 103 even at a high temperature of 573 K; a high voltage resistance such that a voltage can be applied at least within a range of ?40 V to 10 V; and a low on-resistance characteristic such that a current begins to flow at no greater than 5 V.
    Type: Application
    Filed: January 30, 2013
    Publication date: February 5, 2015
    Inventors: Yoshihiro Irokawa, Kiyoshi Shimamura, Encarnacion Antonia Garcia Villora
  • Publication number: 20120067410
    Abstract: A Schottky-barrier junction element 1 has a Schottky-barrier junction between an organic semiconductor 3 and an organic conductor 4. The inorganic semiconductor 3 is any one of nitride semiconductors, Si, GaAs, CdS, CdTe, CuInGaSe, InSb, PbTe, PbS, Ge, InN, GaSb, and SiC. A solar cell uses this Schottky-barrier junction element 1, with its photoelectric conversion section including the Schottky junction. A photoelectric conversion element uses this Schottky-barrier junction element 1, with its conversion section for interconverting light and electricity including the Schottky junction.
    Type: Application
    Filed: March 29, 2010
    Publication date: March 22, 2012
    Applicant: NATIONAL INSTITUTE FOR MATERIALS SCIENCE
    Inventors: Nobuyuki Matsuki, Yoshihiro Irokawa, Kenji Itaka, Hideomi Koinuma, Masatomo Sumiya
  • Patent number: 7011707
    Abstract: A reaction prevention layer is formed to prevent Si from reacting with a gallium nitride group semiconductor (semiconductor crystal A) which is deposited after the reaction prevention layer is formed. By forming a reaction prevention layer comprising a material whose melting point or thermal stability is higher than that of a gallium nitride group semiconductor, e.g., AlN, on a sacrifice layer, a reaction part is not formed in the semiconductor substrate deposited on the reaction prevention layer when the gallium nitride group semiconductor is grown by crystal growth for a long time. In short, owing to the effect that the reaction prevention layer prevents silicon (Si) from diffusing, the reaction part is generated only in the sacrifice layer and it is never formed at the upper portion of the reaction prevention layer even by growing the semiconductor crystal A at a high temperature for a long time.
    Type: Grant
    Filed: March 27, 2002
    Date of Patent: March 14, 2006
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Seiji Nagai, Kazuyoshi Tomita, Yoshihiro Irokawa, Kenji Ito
  • Patent number: 6914273
    Abstract: A GaN based enhancement mode MOSFET includes a GaN layer and a (Group III)xGa1?xN layer, such as an AlxGa1?xN disposed on the GaN layer. The thickness of the AlxGa1?xN layer is less than 20 nm to provide a negligible sheet carrier concentration in the GaN layer along its interface with AlxGa1?xN. A source and a drain region extend through the AlxGa1?xN layer into the GaN layer, the source and drain region separated by a channel region. A gate dielectric is disposed over the channel region. A gate electrode is disposed on the gate dielectric. The MOSFET formed is a true enhancement MOSFET which is in an off state when the gate is unbiased.
    Type: Grant
    Filed: August 26, 2003
    Date of Patent: July 5, 2005
    Assignee: University of Florida Research Foundation, Inc.
    Inventors: Fan Ren, Cammy Rene Abernathy, Stephen J. Pearton, Yoshihiro Irokawa
  • Publication number: 20040115937
    Abstract: A reaction prevention layer is formed to prevent Si from reacting with a gallium nitride group semiconductor (semiconductor crystal A) which is deposited after the reaction prevention layer is formed. By forming a reaction prevention layer comprising a material whose melting point or thermal stability is higher than that of a gallium nitride group semiconductor, e.g., AlN, on a sacrifice layer, a reaction part is not formed in the semiconductor substrate deposited on the reaction prevention layer when the gallium nitride group semiconductor is grown by crystal growth for a long time. In short, owing to the effect that the reaction prevention layer prevents silicon (Si) from diffusing, the reaction part is generated only in the sacrifice layer and it is never formed at the upper portion of the reaction prevention layer even by growing the semiconductor crystal A at a high temperature for a long time.
    Type: Application
    Filed: January 8, 2004
    Publication date: June 17, 2004
    Inventors: Seiji Nagai, Kazuyoshi Tomita, Yoshihiro Irokawa, Kenji Ito
  • Publication number: 20040077166
    Abstract: Hydrogen ion (H+) is injected into a Si (111) substrate (base substrate) 10 at the approximately ambient temperature at a doping rate of 1×1016/cm2 and at an accelerating voltage of 10 keV. As a result, an ion injection layer whose ion concentration is locally high is formed at the depth h≈100 nm from the surface (ion injection plane) by injecting ion. About 300 nm of AlGaN buffer layer 20 is formed on the ion injection front of the Si substrate 10, and about 200 &mgr;m of gallium nitride (GaN) layer 30 is deposited thereon as an objective semiconductor crystal. In this crystal growing process, the Si substrate 10 is ruptured at the ion injection layer and is finally separated into about 100 nm of thin film part 11 and a main part of the Si substrate 10. According to this method for producing a semiconductor crystal, a single crystalline gallium nitride (GaN) which has more excellent crystallinity and less cracks than a conventional one can be obtained.
    Type: Application
    Filed: September 29, 2003
    Publication date: April 22, 2004
    Inventors: Seiji Nagal, Kazuyoshi Tomita, Yoshihiro Irokawa, Tetsu Kachi
  • Publication number: 20040041169
    Abstract: A GaN based enhancement mode MOSFET includes a GaN layer and a (Group III)xGa1-xN layer, such as an AlxGa1-xN disposed on the GaN layer. The thickness of the AlxGa1-xN layer is less than 20 nm to provide a negligible sheet carrier concentration in the GaN layer along its interface with AlxGa1-xN. A source and a drain region extend through the AlxGa1-xN layer into the GaN layer, the source and drain region separated by a channel region. A gate dielectric is disposed over the channel region. A gate electrode is disposed on the gate dielectric. The MOSFET formed is a true enhancement MOSFET which is in an off state when the gate is unbiased.
    Type: Application
    Filed: August 26, 2003
    Publication date: March 4, 2004
    Inventors: Fan Ren, Cammy Rene Abernathy, Stephen J. Pearton, Yoshihiro Irokawa