Patents by Inventor Yoshihiro Kanno

Yoshihiro Kanno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11822274
    Abstract: A fixing device includes an annular belt having an outer circumferential surface, and a facing member that faces the outer circumferential surface of the annular belt to form a nip region. The annular belt is configured so that in measurement of a hardness of the outer circumferential surface using a hardness tester, a ratio (A/B) of a first hardness value (A) to a second hardness value (B) is 0.738 or more and 0.837 or less. The first hardness value (A) represents a measured value at a time when a measurement time corresponding to a time required for a predetermined point on the outer circumferential surface to pass through the nip region has elapsed after start of the hardness measurement. The second hardness value (B) represents a measured value at a time when the measured value by the hardness tester is saturated.
    Type: Grant
    Filed: December 16, 2022
    Date of Patent: November 21, 2023
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Yoshihiro Kanno
  • Publication number: 20230305464
    Abstract: A fixing device includes an annular belt having an outer circumferential surface, and a facing member that faces the outer circumferential surface of the annular belt to form a nip region. The annular belt is configured so that in measurement of a hardness of the outer circumferential surface using a hardness tester, a ratio (A/B) of a first hardness value (A) to a second hardness value (B) is 0.738 or more and 0.837 or less. The first hardness value (A) represents a measured value at a time when a measurement time corresponding to a time required for a predetermined point on the outer circumferential surface to pass through the nip region has elapsed after start of the hardness measurement. The second hardness value (B) represents a measured value at a time when the measured value by the hardness tester is saturated.
    Type: Application
    Filed: December 16, 2022
    Publication date: September 28, 2023
    Applicant: Oki Electric Industry Co., Ltd.
    Inventor: Yoshihiro KANNO
  • Patent number: 10461163
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. Memory stack structures are located in a memory array region, each of which includes a memory film and a vertical semiconductor channel. Contact via structures located in the terrace region and contact a respective one of the electrically conductive layers. Each of the electrically conductive layers has a respective first thickness throughout the memory array region and includes a contact portion having a respective second thickness that is greater than the respective first thickness within a terrace region. The greater thickness of the contact portion prevents an etch-through during formation of contact via cavities for forming the contact via structures.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: October 29, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Senaka Krishna Kanakamedala, Yoshihiro Kanno, Raghuveer S. Makala, Yanli Zhang, Jin Liu, Murshed Chowdhury, Yao-Sheng Lee
  • Patent number: 10453854
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. Memory stack structures are located in a memory array region, each of which includes a memory film and a vertical semiconductor channel. Contact via structures located in the terrace region and contact a respective one of the electrically conductive layers. Each of the electrically conductive layers has a respective first thickness throughout the memory array region and includes a contact portion having a respective second thickness that is greater than the respective first thickness within a terrace region. The greater thickness of the contact portion prevents an etch-through during formation of contact via cavities for forming the contact via structures.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: October 22, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yoshihiro Kanno, Senaka Krishna Kanakamedala, Raghuveer S. Makala, Yanli Zhang, Jin Liu, Murshed Chowdhury
  • Publication number: 20190148392
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. Memory stack structures are located in a memory array region, each of which includes a memory film and a vertical semiconductor channel. Contact via structures located in the terrace region and contact a respective one of the electrically conductive layers. Each of the electrically conductive layers has a respective first thickness throughout the memory array region and includes a contact portion having a respective second thickness that is greater than the respective first thickness within a terrace region. The greater thickness of the contact portion prevents an etch-through during formation of contact via cavities for forming the contact via structures.
    Type: Application
    Filed: November 15, 2017
    Publication date: May 16, 2019
    Inventors: Yoshihiro KANNO, Senaka Krishna KANAKAMEDALA, Raghuveer S. MAKALA, Yanli ZHANG, Jin LIU, Murshed CHOWDHURY
  • Publication number: 20190148506
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. Memory stack structures are located in a memory array region, each of which includes a memory film and a vertical semiconductor channel. Contact via structures located in the terrace region and contact a respective one of the electrically conductive layers. Each of the electrically conductive layers has a respective first thickness throughout the memory array region and includes a contact portion having a respective second thickness that is greater than the respective first thickness within a terrace region. The greater thickness of the contact portion prevents an etch-through during formation of contact via cavities for forming the contact via structures.
    Type: Application
    Filed: November 15, 2017
    Publication date: May 16, 2019
    Inventors: Senaka Krishna KANAKAMEDALA, Yoshihiro KANNO, Raghuveer S. MAKALA, Yanli ZHANG, Jin LIU, Murshed CHOWDHURY, Yao-Sheng LEE
  • Patent number: 10156744
    Abstract: A display device in an embodiment according to the present invention includes a display region arranged above a flexible substrate, the display region including a first display region and a second display region continuing from the first display region, at least the second display region including a curved surface. The second display region is located at a position where an image displayed in the second display region is not seen directly when viewing the first display region from a perpendicular direction with respect to a center part of the first display region.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: December 18, 2018
    Assignee: Japan Display Inc.
    Inventors: Naohisa Andou, Tomoki Nakamura, Yoshihiro Kanno
  • Publication number: 20180173153
    Abstract: A cleaning blade for removing residual toner on a surface of an image carrier, includes a fixed part to be held by a holder; and a free length part that is not held by the holder. Rebound resilience at 25° C. of a material of the cleaning blade is not lower than 11% and not higher than 36%, and an amount of plastic deformation at 25° C. of the material is not greater than 2.4 N×mm.
    Type: Application
    Filed: December 18, 2017
    Publication date: June 21, 2018
    Inventor: Yoshihiro KANNO
  • Publication number: 20170097535
    Abstract: A display device in an embodiment according to the present invention includes a display region arranged above a flexible substrate, the display region including a first display region and a second display region continuing from the first display region, at least the second display region including a curved surface. The second display region is located at a position where an image displayed in the second display region is not seen directly when viewing the first display region from a perpendicular direction with respect to a center part of the first display region.
    Type: Application
    Filed: September 21, 2016
    Publication date: April 6, 2017
    Inventors: Naohisa ANDOU, Tomoki NAKAMURA, Yoshihiro KANNO
  • Patent number: 8531632
    Abstract: A display device formed by plural pixels that have reflective regions and transmissive regions is disclosed. The display device includes, in each of the pixels: an element layer formed on a substrate; a planarizing layer formed on the substrate to cover the element layer; and a gap adjusting layer formed on the planarizing layer on the element layer. In the display device, the reflective region is formed by an area including the element layer, the planarizing layer, the gap adjusting layer, and a reflection electrode formed on the gap adjusting layer, and the transmissive region is formed by an area including the planarizing layer formed on the substrate excluding an area in which the gap adjusting layer is formed.
    Type: Grant
    Filed: April 6, 2012
    Date of Patent: September 10, 2013
    Assignee: Japan Display West Inc.
    Inventors: Takeo Koito, Yoshihiro Kanno, Morikazu Nomura
  • Publication number: 20120196031
    Abstract: A display device formed by plural pixels that have reflective regions and transmissive regions is disclosed. The display device includes, in each of the pixels: an element layer formed on a substrate; a planarizing layer formed on the substrate to cover the element layer; and a gap adjusting layer formed on the planarizing layer on the element layer. In the display device, the reflective region is formed by an area including the element layer, the planarizing layer, the gap adjusting layer, and a reflection electrode formed on the gap adjusting layer, and the transmissive region is formed by an area including the planarizing layer formed on the substrate excluding an area in which the gap adjusting layer is formed.
    Type: Application
    Filed: April 6, 2012
    Publication date: August 2, 2012
    Applicant: Sony Corporation
    Inventors: Takeo KOITO, Yoshihiro KANNO, Morikazu NOMURA
  • Patent number: 8189145
    Abstract: A display device formed by plural pixels that have reflective regions and transmissive regions is disclosed. The display device includes, in each of the pixels: an element layer formed on a substrate; a planarizing layer formed on the substrate to cover the element layer; and a gap adjusting layer formed on the planarizing layer on the element layer. In the display device, the reflective region is formed by an area including the element layer, the planarizing layer, the gap adjusting layer, and a reflection electrode formed on the gap adjusting layer, and the transmissive region is formed by an area including the planarizing layer formed on the substrate excluding an area in which the gap adjusting layer is formed.
    Type: Grant
    Filed: November 30, 2007
    Date of Patent: May 29, 2012
    Assignee: Sony Corporation
    Inventors: Takeo Koito, Yoshihiro Kanno, Morikazu Nomura
  • Publication number: 20080151158
    Abstract: A display device formed by plural pixels that have reflective regions and transmissive regions is disclosed. The display device includes, in each of the pixels: an element layer formed on a substrate; a planarizing layer formed on the substrate to cover the element layer; and a gap adjusting layer formed on the planarizing layer on the element layer. In the display device, the reflective region is formed by an area including the element layer, the planarizing layer, the gap adjusting layer, and a reflection electrode formed on the gap adjusting layer, and the transmissive region is formed by an area including the planarizing layer formed on the substrate excluding an area in which the gap adjusting layer is formed.
    Type: Application
    Filed: November 30, 2007
    Publication date: June 26, 2008
    Applicant: SONY CORPORATION
    Inventors: Takeo Koito, Yoshihiro Kanno, Morikazu Nomura
  • Patent number: 6707250
    Abstract: A liquid crystal cell substrate 109, a plasma cell substrate 104, a dielectric layer 103 provided between the liquid crystal cell substrate 109 and the plasma cell substrate 104, a liquid crystal layer 110 provided between the liquid crystal cell substrate 109 and the dielectric layer 103, and a plurality of plasma channels 106 provided between the dielectric layer 103 and the plasma cell substrate 104, are provided. Each of the plurality of plasma channels 106 includes a discharge gas, an anode 107 and a cathode 108, and the cathode 108 includes a cathode layer 108a made of a mixture of a conductive material and an insulative material including a glass having a lead weight percentage of 30% or less.
    Type: Grant
    Filed: June 7, 2001
    Date of Patent: March 16, 2004
    Assignees: Sharp Kabushiki Kaisha, Sony Corporation
    Inventors: Kiyoshi Okano, Yoshihiro Kanno, Yoichi Morita, Takahiro Togawa, Hirohito Komatsu, Masatake Hayashi, Atsushi Seki
  • Patent number: 6597332
    Abstract: A plasma addressing display device comprising a flat panel including a display cell having columns of signal electrodes and also including a plasma cell having rows of discharge channels, with pixels formed at intersections of the signal electrodes and the discharge channels; a scanning circuit for sequentially discharging the columns of the signal electrodes at a pre-set period to select pixels from row to row; and a signal circuit for supplying picture signals to the column of the signal electrodes to write the picture signals in the pixels of the selected row, the scanning circuit discharging each discharge channel with time shift as the discharging period allocated to the discharge channel of a previous row is partially overlapped at least with the discharging period allocated to the discharge channel of the next row to allocate a discharging period longer than the pre-set period to each discharge channel.
    Type: Grant
    Filed: July 26, 2000
    Date of Patent: July 22, 2003
    Assignees: Sony Corporation, Sharp Kabushiki Kaisha
    Inventors: Yoshihiro Kanno, Yoichi Morita, Takahiro Togawa, Hirohito Komatsu, Masatake Hayashi, Kiyoshi Okano
  • Publication number: 20030057830
    Abstract: A plasma cell constituting a display device includes a pair of substrates, bonded to each other with a pre-set gap in-between for defining a hermetically sealed space in-between, an ionizable gas charged into the space and discharge electrodes formed on at least one of the substrates for ionizing the gas for producing electrical discharge in the space. The discharge electrodes are overcoated by a film-shaped substance formed by an electro-deposition method. This substance has resistance against sputtering for protecting the discharge electrodes against impacts by the ionized gas and secondary electron emitting characteristics enabling electrical discharge. The substance is selected from the group of borides, carbides, oxides, nitrides, metals and metalloids., and has sufficient resistance against sputtering to eliminate or suppress the amount of mercury used.
    Type: Application
    Filed: December 30, 1999
    Publication date: March 27, 2003
    Inventor: YOSHIHIRO KANNO
  • Publication number: 20020036465
    Abstract: A liquid crystal cell substrate 109, a plasma cell substrate 104, a dielectric layer 103 provided between the liquid crystal cell substrate 109 and the plasma cell substrate 104, a liquid crystal layer 110 provided between the liquid crystal cell substrate 109 and the dielectric layer 103, and a plurality of plasma channels 106 provided between the dielectric layer 103 and the plasma cell substrate 104, are provided. Each of the plurality of plasma channels 106 includes a discharge gas, an anode 107 and a cathode 108, and the cathode 108 includes a cathode layer 108a made of a mixture of a conductive material and an insulative material including a glass having a lead weight percentage of 30% or less.
    Type: Application
    Filed: June 7, 2001
    Publication date: March 28, 2002
    Inventors: Kiyoshi Okano, Yoshihiro Kanno, Yoichi Morita, Takahiro Togawa, Hirohito Komatsu, Masatake Hayashi, Atsushi Seki
  • Publication number: 20020021080
    Abstract: A display apparatus includes a pair of substrates connected to each other via a pre-set gap for delimiting a hermetically sealed space, an ionizable gas charged into this space, and discharging electrodes formed at least on one of the substrates to incur discharge in the space. The discharging electrodes are coated with a protective skin film formed by the electro-deposition method. The protective skin film is an electro-deposited and sintered mixture of boride or carbon containing electrically conductive powders and glass powders. In electro-deposition, the mean particle size of the electrically conductive powders and the glass powders is not larger than 10 &mgr;m or in a range from 1 to 3 &mgr;m. The electrically conductive powders and the glass powders are mixed in a volumetric ratio in a range from 9:1 to 3:7, with the film thickness of the protective skin film being in a range from 1 to 20 &mgr;m.
    Type: Application
    Filed: April 27, 2001
    Publication date: February 21, 2002
    Inventors: Yoshihiro Kanno, Yoichi Morita, Masatake Hayashi, Hirohito Komatsu, Kiyoshi Okano
  • Patent number: 5695657
    Abstract: A magneto-resistance effect type thin-film magnetic head for detecting reproduced signals by the magneto-resistance effect, which is suitable for detecting reproduced signals by magneto-resistance effects, is disclosed. The thin-film magnetic head includes a two-layered magneto-resistance effect element made up of a first magneto-resistance effect film and a second magneto-resistance effect film of substantially the same width as the first magneto-resistance effect film, layered with a non-magnetic insulating film in-between. Since the magneto-static coupling is produced between the first and second MR films, the magnetic state between the first and second MR films is stabilized. The film thickness contributing to the playback output can be reduced as in the case of a single-layer magnetic head constituted by a single-layer MR film for realizing a high playback output.
    Type: Grant
    Filed: June 27, 1996
    Date of Patent: December 9, 1997
    Assignee: Sony Corporation
    Inventors: Takuji Shibata, Yoshihiro Kanno, Tadayuki Honda, Akio Takada, Yukio Kondo, Tadao Suzuki
  • Patent number: 4404423
    Abstract: A three-phase gas insulated bus has three high voltage conductors inside a grounded cylindrical metal sheath filled with an insulating gas. The conductors are integrally supported by a single spacer having three supporting parts. The spacer is radially slidably coupled with the inner wall of the sheath.
    Type: Grant
    Filed: September 24, 1981
    Date of Patent: September 13, 1983
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Takaaki Sakakibara, Yoshihiro Kanno