Patents by Inventor Yoshihiro Kusuyama
Yoshihiro Kusuyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9330940Abstract: There are provided a structure of a semiconductor device in which low power consumption is realized even in a case where a size of a display region is increased to be a large size screen and a manufacturing method thereof. A gate electrode in a pixel portion is formed as a three layered structure of a material film containing mainly W, a material film containing mainly Al, and a material film containing mainly Ti to reduce a wiring resistance. A wiring is etched using an IPC etching apparatus. The gate electrode has a taper shape and the width of a region which becomes the taper shape is set to be 1 ?m or more.Type: GrantFiled: May 23, 2014Date of Patent: May 3, 2016Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hideomi Suzawa, Yoshihiro Kusuyama, Koji Ono, Jun Koyama
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Patent number: 9142574Abstract: For forming a gate electrode, a conductive film with low resistance including Al or a material containing Al as its main component and a conductive film with low contact resistance for preventing diffusion of Al into a semiconductor layer are laminated, and the gate electrode is fabricated by using an apparatus which is capable of performing etching treatment at high speed.Type: GrantFiled: December 16, 2014Date of Patent: September 22, 2015Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hideomi Suzawa, Koji Ono, Yoshihiro Kusuyama
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Publication number: 20150099333Abstract: For forming a gate electrode, a conductive film with low resistance including Al or a material containing Al as its main component and a conductive film with low contact resistance for preventing diffusion of Al into a semiconductor layer are laminated, and the gate electrode is fabricated by using an apparatus which is capable of performing etching treatment at high speed.Type: ApplicationFiled: December 16, 2014Publication date: April 9, 2015Inventors: Shunpei Yamazaki, Hideomi Suzawa, Koji Ono, Yoshihiro Kusuyama
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Patent number: 8921169Abstract: For forming a gate electrode, a conductive film with low resistance including Al or a material containing Al as its main component and a conductive film with low contact resistance for preventing diffusion of Al into a semiconductor layer are laminated, and the gate electrode is fabricated by using an apparatus which is capable of performing etching treatment at high speed.Type: GrantFiled: May 9, 2013Date of Patent: December 30, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hideomi Suzawa, Koji Ono, Yoshihiro Kusuyama
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Publication number: 20140256116Abstract: There are provided a structure of a semiconductor device in which low power consumption is realized even in a case where a size of a display region is increased to be a large size screen and a manufacturing method thereof. A gate electrode in a pixel portion is formed as a three layered structure of a material film containing mainly W, a material film containing mainly Al, and a material film containing mainly Ti to reduce a wiring resistance. A wiring is etched using an IPC etching apparatus. The gate electrode has a taper shape and the width of a region which becomes the taper shape is set to be 1 ?m or more.Type: ApplicationFiled: May 23, 2014Publication date: September 11, 2014Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hideomi Suzawa, Yoshihiro Kusuyama, Koji Ono, Jun Koyama
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Patent number: 8735889Abstract: There are provided a structure of a semiconductor device in which low power consumption is realized even in a case where a size of a display region is increased to be a large size screen and a manufacturing method thereof. A gate electrode in a pixel portion is formed as a three layered structure of a material film containing mainly W, a material film containing mainly Al, and a material film containing mainly Ti to reduce a wiring resistance. A wiring is etched using an IPC etching apparatus. The gate electrode has a taper shape and the width of a region which becomes the taper shape is set to be 1 ?m or more.Type: GrantFiled: November 1, 2011Date of Patent: May 27, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hideomi Suzawa, Yoshihiro Kusuyama, Koji Ono, Jun Koyama
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Publication number: 20130252385Abstract: For forming a gate electrode, a conductive film with low resistance including Al or a material containing Al as its main component and a conductive film with low contact resistance for preventing diffusion of Al into a semiconductor layer are laminated, and the gate electrode is fabricated by using an apparatus which is capable of performing etching treatment at high speed.Type: ApplicationFiled: May 9, 2013Publication date: September 26, 2013Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hideomi Suzawa, Koji Ono, Yoshihiro Kusuyama
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Patent number: 8461596Abstract: The present invention has an object to provide an active-matrix liquid crystal display device that realizes the improvement in productivity as well as in yield. In the present invention, a laminate film comprising the conductive film comprising metallic material and the second amorphous semiconductor film containing an impurity element of one conductivity type and the amorphous semiconductor film is selectively etched with the same etching gas to form a side edge of the first amorphous semiconductor film 1001 into a taper shape. Thereby, a coverage problem of a pixel electrode 1003 can be solved and an inverse stagger type TFT can be completed with three photomask.Type: GrantFiled: November 3, 2011Date of Patent: June 11, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hideomi Suzawa, Yoshihiro Kusuyama, Shunpei Yamazaki
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Patent number: 8440484Abstract: For forming a gate electrode, a conductive film with low resistance including Al or a material containing Al as its main component and a conductive film with low contact resistance for preventing diffusion of Al into a semiconductor layer are laminated, and the gate electrode is fabricated by using an apparatus which is capable of performing etching treatment at high speed.Type: GrantFiled: June 22, 2012Date of Patent: May 14, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hideomi Suzawa, Koji Ono, Yoshihiro Kusuyama
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Publication number: 20120264245Abstract: For forming a gate electrode, a conductive film with low resistance including Al or a material containing Al as its main component and a conductive film with low contact resistance for preventing diffusion of Al into a semiconductor layer are laminated, and the gate electrode is fabricated by using an apparatus which is capable of performing etching treatment at high speed.Type: ApplicationFiled: June 22, 2012Publication date: October 18, 2012Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei YAMAZAKI, Hideomi SUZAWA, Koji ONO, Yoshihiro KUSUYAMA
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Patent number: 8207536Abstract: For forming a gate electrode, a conductive film with low resistance including Al or a material containing Al as its main component and a conductive film with low contact resistance for preventing diffusion of Al into a semiconductor layer are laminated, and the gate electrode is fabricated by using an apparatus which is capable of performing etching treatment at high speed.Type: GrantFiled: May 10, 2011Date of Patent: June 26, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hideomi Suzawa, Koji Ono, Yoshihiro Kusuyama
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Publication number: 20120043580Abstract: There are provided a structure of a semiconductor device in which low power consumption is realized even in a case where a size of a display region is increased to be a large size screen and a manufacturing method thereof. A gate electrode in a pixel portion is formed as a three layered structure of a material film containing mainly W, a material film containing mainly Al, and a material film containing mainly Ti to reduce a wiring resistance. A wiring is etched using an IPC etching apparatus. The gate electrode has a taper shape and the width of a region which becomes the taper shape is set to be 1 ?m or more.Type: ApplicationFiled: November 1, 2011Publication date: February 23, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shunpei Yamazaki, Hideomi Suzawa, Yoshihiro Kusuyama, Koji Ono, Jun Koyama
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Publication number: 20120043544Abstract: The present invention has an object to provide an active-matrix liquid crystal display device that realizes the improvement in productivity as well as in yield. In the present invention, a laminate film comprising the conductive film comprising metallic material and the second amorphous semiconductor film containing an impurity element of one conductivity type and the amorphous semiconductor film is selectively etched with the same etching gas to form a side edge of the first amorphous semiconductor film 1001 into a taper shape. Thereby, a coverage problem of a pixel electrode 1003 can be solved and an inverse stagger type TFT can be completed with three photomask. Selected figure is FIG. 15.Type: ApplicationFiled: November 3, 2011Publication date: February 23, 2012Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Hideomi SUZAWA, Yoshihiro KUSUYAMA, Shunpei YAMAZAKI
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Patent number: 8093591Abstract: It is an object of the present invention to provide a manufacturing method of semiconductor device whereby the number of processes is decreased due to simultaneously forming a contact hole in a lamination film of different material and film thickness (inorganic insulating film and organic resin film) by conducting etching once. By setting the selective ratio of dry etching (etching rate of organic resin film 503/etching rate of inorganic insulating film 502 containing nitrogen) from 1.6 to 2.9, preferably 1.9, the shape and the size of the contact holes to be formed even in a film of different material and film thickness can be nearly the same in both of the contact holes.Type: GrantFiled: December 14, 2009Date of Patent: January 10, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hideomi Suzawa, Yoshihiro Kusuyama
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Patent number: 8053339Abstract: There are provided a structure of a semiconductor device in which low power consumption is realized even in a case where a size of a display region is increased to be a large size screen and a manufacturing method thereof. A gate electrode in a pixel portion is formed as a three layered structure of a material film containing mainly W, a material film containing mainly Al, and a material film containing mainly Ti to reduce a wiring resistance. A wiring is etched using an IPC etching apparatus. The gate electrode has a taper shape and the width of a region which becomes the taper shape is set to be 1 ?m or more.Type: GrantFiled: May 21, 2008Date of Patent: November 8, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hideomi Suzawa, Yoshihiro Kusuyama, Koji Ono, Jun Koyama
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Patent number: 8053781Abstract: The present invention has an object to provide an active-matrix liquid crystal display device that realizes the improvement in productivity as well as in yield. In the present invention, a laminate film comprising the conductive film comprising metallic material and the second amorphous semiconductor film containing an impurity element of one conductivity type and the amorphous semiconductor film is selectively etched with the same etching gas to form a side edge of the first amorphous semiconductor film 1001 into a taper shape. Thereby, a coverage problem of a pixel electrode 1003 can be solved and an inverse stagger type TFT can be completed with three photomask. Selected figure is FIG. 15.Type: GrantFiled: January 20, 2011Date of Patent: November 8, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hideomi Suzawa, Yoshihiro Kusuyama, Shunpei Yamazaki
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Publication number: 20110210336Abstract: For forming a gate electrode, a conductive film with low resistance including Al or a material containing Al as its main component and a conductive film with low contact resistance for preventing diffusion of Al into a semiconductor layer are laminated, and the gate electrode is fabricated by using an apparatus which is capable of performing etching treatment at high speed.Type: ApplicationFiled: May 10, 2011Publication date: September 1, 2011Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shunpei Yamazaki, Hideomi Suzawa, Koji Ono, Yoshihiro Kusuyama
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Patent number: 7952152Abstract: For forming a gate electrode, a conductive film with low resistance including Al or a material containing Al as its main component and a conductive film with low contact resistance for preventing diffusion of Al into a semiconductor layer are laminated, and the gate electrode is fabricated by using an apparatus which is capable of performing etching treatment at high speed.Type: GrantFiled: August 4, 2010Date of Patent: May 31, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hideomi Suzawa, Koji Ono, Yoshihiro Kusuyama
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Publication number: 20110114959Abstract: The present invention has an object to provide an active-matrix liquid crystal display device that realizes the improvement in productivity as well as in yield. In the present invention, a laminate film comprising the conductive film comprising metallic material and the second amorphous semiconductor film containing an impurity element of one conductivity type and the amorphous semiconductor film is selectively etched with the same etching gas to form a side edge of the first amorphous semiconductor film 1001 into a taper shape. Thereby, a coverage problem of a pixel electrode 1003 can be solved and an inverse stagger type TFT can be completed with three photomask. Selected figure is FIG. 15.Type: ApplicationFiled: January 20, 2011Publication date: May 19, 2011Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Hideomi SUZAWA, Yoshihiro KUSUYAMA, Shunpei YAMAZAKI
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Patent number: 7884369Abstract: The wiring of the present invention has a layered structure that includes a first conductive layer (first layer) having a first width and made of one or a plurality of kinds of elements selected from W and Mo, or an alloy or compound mainly containing the element, a low-resistant second conductive layer (second layer) having a second width smaller than the first width, and made of an alloy or a compound mainly containing Al, and a third conductive layer (third layer) having a third width smaller than the second width, and made of an alloy or compound mainly containing Ti. With this constitution, the present invention is fully ready for enlargement of a pixel portion. At least edges of the second conductive layer have a taper-shaped cross-section. Because of this shape, satisfactory coverage can be obtained.Type: GrantFiled: September 22, 2006Date of Patent: February 8, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hideomi Suzawa, Koji Ono, Yoshihiro Kusuyama