Patents by Inventor Yoshihiro Kusuyama

Yoshihiro Kusuyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9330940
    Abstract: There are provided a structure of a semiconductor device in which low power consumption is realized even in a case where a size of a display region is increased to be a large size screen and a manufacturing method thereof. A gate electrode in a pixel portion is formed as a three layered structure of a material film containing mainly W, a material film containing mainly Al, and a material film containing mainly Ti to reduce a wiring resistance. A wiring is etched using an IPC etching apparatus. The gate electrode has a taper shape and the width of a region which becomes the taper shape is set to be 1 ?m or more.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: May 3, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideomi Suzawa, Yoshihiro Kusuyama, Koji Ono, Jun Koyama
  • Patent number: 9142574
    Abstract: For forming a gate electrode, a conductive film with low resistance including Al or a material containing Al as its main component and a conductive film with low contact resistance for preventing diffusion of Al into a semiconductor layer are laminated, and the gate electrode is fabricated by using an apparatus which is capable of performing etching treatment at high speed.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: September 22, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideomi Suzawa, Koji Ono, Yoshihiro Kusuyama
  • Publication number: 20150099333
    Abstract: For forming a gate electrode, a conductive film with low resistance including Al or a material containing Al as its main component and a conductive film with low contact resistance for preventing diffusion of Al into a semiconductor layer are laminated, and the gate electrode is fabricated by using an apparatus which is capable of performing etching treatment at high speed.
    Type: Application
    Filed: December 16, 2014
    Publication date: April 9, 2015
    Inventors: Shunpei Yamazaki, Hideomi Suzawa, Koji Ono, Yoshihiro Kusuyama
  • Patent number: 8921169
    Abstract: For forming a gate electrode, a conductive film with low resistance including Al or a material containing Al as its main component and a conductive film with low contact resistance for preventing diffusion of Al into a semiconductor layer are laminated, and the gate electrode is fabricated by using an apparatus which is capable of performing etching treatment at high speed.
    Type: Grant
    Filed: May 9, 2013
    Date of Patent: December 30, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideomi Suzawa, Koji Ono, Yoshihiro Kusuyama
  • Publication number: 20140256116
    Abstract: There are provided a structure of a semiconductor device in which low power consumption is realized even in a case where a size of a display region is increased to be a large size screen and a manufacturing method thereof. A gate electrode in a pixel portion is formed as a three layered structure of a material film containing mainly W, a material film containing mainly Al, and a material film containing mainly Ti to reduce a wiring resistance. A wiring is etched using an IPC etching apparatus. The gate electrode has a taper shape and the width of a region which becomes the taper shape is set to be 1 ?m or more.
    Type: Application
    Filed: May 23, 2014
    Publication date: September 11, 2014
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideomi Suzawa, Yoshihiro Kusuyama, Koji Ono, Jun Koyama
  • Patent number: 8735889
    Abstract: There are provided a structure of a semiconductor device in which low power consumption is realized even in a case where a size of a display region is increased to be a large size screen and a manufacturing method thereof. A gate electrode in a pixel portion is formed as a three layered structure of a material film containing mainly W, a material film containing mainly Al, and a material film containing mainly Ti to reduce a wiring resistance. A wiring is etched using an IPC etching apparatus. The gate electrode has a taper shape and the width of a region which becomes the taper shape is set to be 1 ?m or more.
    Type: Grant
    Filed: November 1, 2011
    Date of Patent: May 27, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideomi Suzawa, Yoshihiro Kusuyama, Koji Ono, Jun Koyama
  • Publication number: 20130252385
    Abstract: For forming a gate electrode, a conductive film with low resistance including Al or a material containing Al as its main component and a conductive film with low contact resistance for preventing diffusion of Al into a semiconductor layer are laminated, and the gate electrode is fabricated by using an apparatus which is capable of performing etching treatment at high speed.
    Type: Application
    Filed: May 9, 2013
    Publication date: September 26, 2013
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideomi Suzawa, Koji Ono, Yoshihiro Kusuyama
  • Patent number: 8461596
    Abstract: The present invention has an object to provide an active-matrix liquid crystal display device that realizes the improvement in productivity as well as in yield. In the present invention, a laminate film comprising the conductive film comprising metallic material and the second amorphous semiconductor film containing an impurity element of one conductivity type and the amorphous semiconductor film is selectively etched with the same etching gas to form a side edge of the first amorphous semiconductor film 1001 into a taper shape. Thereby, a coverage problem of a pixel electrode 1003 can be solved and an inverse stagger type TFT can be completed with three photomask.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: June 11, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideomi Suzawa, Yoshihiro Kusuyama, Shunpei Yamazaki
  • Patent number: 8440484
    Abstract: For forming a gate electrode, a conductive film with low resistance including Al or a material containing Al as its main component and a conductive film with low contact resistance for preventing diffusion of Al into a semiconductor layer are laminated, and the gate electrode is fabricated by using an apparatus which is capable of performing etching treatment at high speed.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: May 14, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideomi Suzawa, Koji Ono, Yoshihiro Kusuyama
  • Publication number: 20120264245
    Abstract: For forming a gate electrode, a conductive film with low resistance including Al or a material containing Al as its main component and a conductive film with low contact resistance for preventing diffusion of Al into a semiconductor layer are laminated, and the gate electrode is fabricated by using an apparatus which is capable of performing etching treatment at high speed.
    Type: Application
    Filed: June 22, 2012
    Publication date: October 18, 2012
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei YAMAZAKI, Hideomi SUZAWA, Koji ONO, Yoshihiro KUSUYAMA
  • Patent number: 8207536
    Abstract: For forming a gate electrode, a conductive film with low resistance including Al or a material containing Al as its main component and a conductive film with low contact resistance for preventing diffusion of Al into a semiconductor layer are laminated, and the gate electrode is fabricated by using an apparatus which is capable of performing etching treatment at high speed.
    Type: Grant
    Filed: May 10, 2011
    Date of Patent: June 26, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideomi Suzawa, Koji Ono, Yoshihiro Kusuyama
  • Publication number: 20120043580
    Abstract: There are provided a structure of a semiconductor device in which low power consumption is realized even in a case where a size of a display region is increased to be a large size screen and a manufacturing method thereof. A gate electrode in a pixel portion is formed as a three layered structure of a material film containing mainly W, a material film containing mainly Al, and a material film containing mainly Ti to reduce a wiring resistance. A wiring is etched using an IPC etching apparatus. The gate electrode has a taper shape and the width of a region which becomes the taper shape is set to be 1 ?m or more.
    Type: Application
    Filed: November 1, 2011
    Publication date: February 23, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei Yamazaki, Hideomi Suzawa, Yoshihiro Kusuyama, Koji Ono, Jun Koyama
  • Publication number: 20120043544
    Abstract: The present invention has an object to provide an active-matrix liquid crystal display device that realizes the improvement in productivity as well as in yield. In the present invention, a laminate film comprising the conductive film comprising metallic material and the second amorphous semiconductor film containing an impurity element of one conductivity type and the amorphous semiconductor film is selectively etched with the same etching gas to form a side edge of the first amorphous semiconductor film 1001 into a taper shape. Thereby, a coverage problem of a pixel electrode 1003 can be solved and an inverse stagger type TFT can be completed with three photomask. Selected figure is FIG. 15.
    Type: Application
    Filed: November 3, 2011
    Publication date: February 23, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Hideomi SUZAWA, Yoshihiro KUSUYAMA, Shunpei YAMAZAKI
  • Patent number: 8093591
    Abstract: It is an object of the present invention to provide a manufacturing method of semiconductor device whereby the number of processes is decreased due to simultaneously forming a contact hole in a lamination film of different material and film thickness (inorganic insulating film and organic resin film) by conducting etching once. By setting the selective ratio of dry etching (etching rate of organic resin film 503/etching rate of inorganic insulating film 502 containing nitrogen) from 1.6 to 2.9, preferably 1.9, the shape and the size of the contact holes to be formed even in a film of different material and film thickness can be nearly the same in both of the contact holes.
    Type: Grant
    Filed: December 14, 2009
    Date of Patent: January 10, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideomi Suzawa, Yoshihiro Kusuyama
  • Patent number: 8053339
    Abstract: There are provided a structure of a semiconductor device in which low power consumption is realized even in a case where a size of a display region is increased to be a large size screen and a manufacturing method thereof. A gate electrode in a pixel portion is formed as a three layered structure of a material film containing mainly W, a material film containing mainly Al, and a material film containing mainly Ti to reduce a wiring resistance. A wiring is etched using an IPC etching apparatus. The gate electrode has a taper shape and the width of a region which becomes the taper shape is set to be 1 ?m or more.
    Type: Grant
    Filed: May 21, 2008
    Date of Patent: November 8, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideomi Suzawa, Yoshihiro Kusuyama, Koji Ono, Jun Koyama
  • Patent number: 8053781
    Abstract: The present invention has an object to provide an active-matrix liquid crystal display device that realizes the improvement in productivity as well as in yield. In the present invention, a laminate film comprising the conductive film comprising metallic material and the second amorphous semiconductor film containing an impurity element of one conductivity type and the amorphous semiconductor film is selectively etched with the same etching gas to form a side edge of the first amorphous semiconductor film 1001 into a taper shape. Thereby, a coverage problem of a pixel electrode 1003 can be solved and an inverse stagger type TFT can be completed with three photomask. Selected figure is FIG. 15.
    Type: Grant
    Filed: January 20, 2011
    Date of Patent: November 8, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideomi Suzawa, Yoshihiro Kusuyama, Shunpei Yamazaki
  • Publication number: 20110210336
    Abstract: For forming a gate electrode, a conductive film with low resistance including Al or a material containing Al as its main component and a conductive film with low contact resistance for preventing diffusion of Al into a semiconductor layer are laminated, and the gate electrode is fabricated by using an apparatus which is capable of performing etching treatment at high speed.
    Type: Application
    Filed: May 10, 2011
    Publication date: September 1, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei Yamazaki, Hideomi Suzawa, Koji Ono, Yoshihiro Kusuyama
  • Patent number: 7952152
    Abstract: For forming a gate electrode, a conductive film with low resistance including Al or a material containing Al as its main component and a conductive film with low contact resistance for preventing diffusion of Al into a semiconductor layer are laminated, and the gate electrode is fabricated by using an apparatus which is capable of performing etching treatment at high speed.
    Type: Grant
    Filed: August 4, 2010
    Date of Patent: May 31, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideomi Suzawa, Koji Ono, Yoshihiro Kusuyama
  • Publication number: 20110114959
    Abstract: The present invention has an object to provide an active-matrix liquid crystal display device that realizes the improvement in productivity as well as in yield. In the present invention, a laminate film comprising the conductive film comprising metallic material and the second amorphous semiconductor film containing an impurity element of one conductivity type and the amorphous semiconductor film is selectively etched with the same etching gas to form a side edge of the first amorphous semiconductor film 1001 into a taper shape. Thereby, a coverage problem of a pixel electrode 1003 can be solved and an inverse stagger type TFT can be completed with three photomask. Selected figure is FIG. 15.
    Type: Application
    Filed: January 20, 2011
    Publication date: May 19, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Hideomi SUZAWA, Yoshihiro KUSUYAMA, Shunpei YAMAZAKI
  • Patent number: 7884369
    Abstract: The wiring of the present invention has a layered structure that includes a first conductive layer (first layer) having a first width and made of one or a plurality of kinds of elements selected from W and Mo, or an alloy or compound mainly containing the element, a low-resistant second conductive layer (second layer) having a second width smaller than the first width, and made of an alloy or a compound mainly containing Al, and a third conductive layer (third layer) having a third width smaller than the second width, and made of an alloy or compound mainly containing Ti. With this constitution, the present invention is fully ready for enlargement of a pixel portion. At least edges of the second conductive layer have a taper-shaped cross-section. Because of this shape, satisfactory coverage can be obtained.
    Type: Grant
    Filed: September 22, 2006
    Date of Patent: February 8, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideomi Suzawa, Koji Ono, Yoshihiro Kusuyama