Abstract: Provided is a differential amplifier circuit having a low current consumption and a small circuit area. The differential amplifier circuit is formed as a drain grounding circuit (source follower circuit), which includes two stages of output transistors that are connected to two stages of amplifier circuits in series, and is configured to control one of the two output transistors by output from the amplifier circuit in the first stage, and to control another of the two output transistors by output from the amplifier circuit in the second stage.

Abstract: Provided is a voltage regulator configured to stably operate with low current consumption, and having good responsiveness. A delay circuit is provided between a transient response improvement circuit and a voltage amplifier circuit.

Abstract: A safe and low-cost voltage regulator is provided through simplification of a circuit configuration of a protection circuit. The voltage regulator has a configuration in which current output of the protection circuit, which serves as a signal indicating that the protection circuit has started to operate, is input to a control circuit configured to improve responsiveness of the voltage regulator.

Abstract: A safe and low-cost voltage regulator is provided through simplification of a circuit configuration of a protection circuit. The voltage regulator has a configuration in which current output of the protection circuit, which serves as a signal indicating that the protection circuit has started to operate, is input to a control circuit configured to improve responsiveness of the voltage regulator.

Abstract: Provided is a voltage regulator configured to stably operate with low current consumption, and having good responsiveness. A delay circuit is provided between a transient response improvement circuit and a voltage amplifier circuit.

Abstract: Provided is a differential amplifier circuit having a low current consumption and a small circuit area. The differential amplifier circuit is formed as a drain grounding circuit (source follower circuit), which includes two stages of output transistors that are connected to two stages of amplifier circuits in series, and is configured to control one of the two output transistors by output from the amplifier circuit in the first stage, and to control another of the two output transistors by output from the amplifier circuit in the second stage.

Abstract: In a pulse width modulation circuit, a multiphase clock generation section generates a multiphase clock signal according to a reference clock. Then, a pulse width modulation signal is generated according to input data and the multiphase clock signal generated by the multiphase clock generation section. The multiphase clock generation section has a phase lock loop circuit and generates the multiphase clock signal by phase-interpolating an intermediate clock signal generated by the phase lock loop circuit.

Abstract: According to an aspect of the invention, there is provided a phase synchronous circuit generating an output signal synchronized with an input signal. The phase synchronous circuit comprises an output circuit putting out an output signal according to an input clock signal, a selection circuit selecting a clock signal applied to the output circuit from multiphase clock signals such that the output circuit puts out an output signal synchronized with the input signal. The internal delay in a phase synchronous circuit using a multiphase clock signal can be efficiently compensated and an output signal synchronized with the reference signal can be generated.

Abstract: In a pulse width modulation circuit, a multiphase clock generation section generates a multiphase clock signal according to a reference clock. Then, a pulse width modulation signal is generated according to input data and the multiphase clock signal generated by the multiphase clock generation section. The multiphase clock generation section has a phase lock loop circuit and generates the multiphase clock signal by phase-interpolating an intermediate clock signal generated by the phase lock loop circuit.

Abstract: According to an aspect of the invention, there is provided a phase synchronous circuit generating an output signal synchronized with an input signal. The phase synchronous circuit comprises an output circuit putting out an output signal according to an input clock signal, a selection circuit selecting a clock signal applied to the output circuit from multiphase clock signals such that the output circuit puts out an output signal synchronized with the input signal. The internal delay in a phase synchronous circuit using a multiphase clock signal can be efficiently compensated and an output signal synchronized with the reference signal can be generated.