Patents by Inventor Yoshihisa Iwata

Yoshihisa Iwata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10256274
    Abstract: According to the embodiment, a semiconductor memory device includes a first conductive layer, a second conductive layer, a first memory cell, a second memory cell, a third conductive layer, a first contact, a intermediate memory cell, a fourth conductive layer, a third memory cell, a fifth conductive layer, and a second contact. The third conductive layer is separated from the first conductive layer and the second conductive layer in a third direction crossing a first direction and crossing a second direction and extends in the second direction. The fifth conductive layer is separated from the second conductive layer in the third direction and extends in the second direction. A first length of the second conductive layer along the second direction is shorter than a second length of the fifth conductive layer along the second direction.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: April 9, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yusuke Kobayashi, Yoshihisa Iwata, Takeshi Sugimoto
  • Patent number: 10199099
    Abstract: A semiconductor memory device includes a first memory cell having a first end connected to a first wiring and a second end connected to a second wiring and a second memory cell having a first end connected to the first wiring and a second end connected to a third wiring. A sense amplifier is configured to: sense a first current flowing in the first wiring when a first voltage is applied to the second and third wirings and a second voltage, larger than the first voltage, is applied to the first wiring; and sense a second current flowing in the first wiring when a third voltage larger than the second voltage is applied to the first wiring, the first voltage to the second wiring, and the second voltage to the third wiring. The sense amplifier reads data according to a difference between the first current and the second current.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: February 5, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Megumu Hori, Yoshihisa Iwata
  • Publication number: 20180337194
    Abstract: A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.
    Type: Application
    Filed: July 27, 2018
    Publication date: November 22, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Tomoo HISHIDA, Yoshihisa IWATA
  • Publication number: 20180277201
    Abstract: A semiconductor memory device includes a first memory cell having a first end connected to a first wiring and a second end connected to a second wiring and a second memory cell having a first end connected to the first wiring and a second end connected to a third wiring. A sense amplifier is configured to: sense a first current flowing in the first wiring when a first voltage is applied to the second and third wirings and a second voltage, larger than the first voltage, is applied to the first wiring; and sense a second current flowing in the first wiring when a third voltage larger than the second voltage is applied to the first wiring, the first voltage to the second wiring, and the second voltage to the third wiring. The sense amplifier reads data according to a difference between the first current and the second current.
    Type: Application
    Filed: September 1, 2017
    Publication date: September 27, 2018
    Inventors: Megumu HORI, Yoshihisa IWATA
  • Patent number: 10068916
    Abstract: A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: September 4, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tomoo Hishida, Yoshihisa Iwata
  • Publication number: 20180175111
    Abstract: According to the embodiment, a semiconductor memory device includes a first conductive layer, a second conductive layer, a first memory cell, a second memory cell, a third conductive layer, a first contact, a intermediate memory cell, a fourth conductive layer, a third memory cell, a fifth conductive layer, and a second contact. The third conductive layer is separated from the first conductive layer and the second conductive layer in a third direction crossing a first direction and crossing a second direction and extends in the second direction. The fifth conductive layer is separated from the second conductive layer in the third direction and extends in the second direction. A first length of the second conductive layer along the second direction is shorter than a second length of the fifth conductive layer along the second direction.
    Type: Application
    Filed: February 20, 2018
    Publication date: June 21, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Yusuke KOBAYASHI, Yoshihisa IWATA, Takeshi SUGIMOTO
  • Patent number: 9929212
    Abstract: According to the embodiment, a semiconductor memory device includes a first conductive layer, a second conductive layer, a first memory cell, a second memory cell, a third conductive layer, a first contact, a intermediate memory cell, a fourth conductive layer, a third memory cell, a fifth conductive layer, and a second contact. The third conductive layer is separated from the first conductive layer and the second conductive layer in a third direction crossing a first direction and crossing a second direction and extends in the second direction. The fifth conductive layer is separated from the second conductive layer in the third direction and extends in the second direction. A first length of the second conductive layer along the second direction is shorter than a second length of the fifth conductive layer along the second direction.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: March 27, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yusuke Kobayashi, Yoshihisa Iwata, Takeshi Sugimoto
  • Patent number: 9886199
    Abstract: According to one embodiment, a magnetic memory device includes a first memory unit including a first memory array and a first drive unit, a second memory unit including a second memory array and a second drive unit, and a controller. The first memory array includes a first magnetic shift register unit. The second memory array includes a second magnetic shift register unit. The controller subdivides input data into a plurality of one-dimensional bit input arrays. The one-dimensional bit input arrays include a first array and a second array. The controller stores the first array in the first magnetic shift register unit on a last in, first out basis, and stores the second array in the second magnetic shift register unit on a last in, first out basis.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: February 6, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsuyoshi Kondo, Hirofumi Morise, Yasuaki Ootera, Takuya Shimada, Michael Amaud Quinsat, Yoshiaki Osada, Yoshihisa Iwata
  • Patent number: 9859211
    Abstract: In a nonvolatile semiconductor memory device, a stacked body is formed by alternately stacking dielectric films and conductive films on a silicon substrate and a plurality of through holes extending in the stacking direction are formed in a matrix configuration. A shunt interconnect and a bit interconnect are provided above the stacked body. Conductor pillars are buried inside the through holes arranged in a line immediately below the shunt interconnect out of the plurality of through holes, and semiconductor pillars are buried inside the remaining through holes. The conductive pillars are formed from a metal, or low resistance silicon. Its upper end portion is connected to the shunt interconnect and its lower end portion is connected to a cell source formed in an upper layer portion of the silicon substrate.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: January 2, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takashi Maeda, Yoshihisa Iwata
  • Patent number: 9679644
    Abstract: A semiconductor storage device includes a variable resistive element, which changes a resistance value according to a polarity and a magnitude of an applied voltage, as a memory element. The semiconductor storage device includes a standby mode in which a power source voltage or a ground voltage is applied to both of a word line and a bit line. The semiconductor storage device includes a data write mode in which a voltage difference equal to or more than a first voltage is applied between the word line and the bit line. The semiconductor storage device includes a read mode in which a voltage difference smaller than the first voltage is applied between the word line and the bit line by changing only one voltage of the word line and the bit line which is applied in the standby mode, and data written in the memory element is read.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: June 13, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takayuki Miyazaki, Reika Ichihara, Kikuko Sugimae, Yoshihisa Iwata
  • Publication number: 20170104002
    Abstract: A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.
    Type: Application
    Filed: December 22, 2016
    Publication date: April 13, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tomoo HISHIDA, Yoshihisa IWATA
  • Publication number: 20170104032
    Abstract: According to the embodiment, a semiconductor memory device includes a first conductive layer, a second conductive layer, a first memory cell, a second memory cell, a third conductive layer, a first contact, a intermediate memory cell, a fourth conductive layer, a third memory cell, a fifth conductive layer, and a second contact. The third conductive layer is separated from the first conductive layer and the second conductive layer in a third direction crossing a first direction and crossing a second direction and extends in the second direction. The fifth conductive layer is separated from the second conductive layer in the third direction and extends in the second direction. A first length of the second conductive layer along the second direction is shorter than a second length of the fifth conductive layer along the second direction.
    Type: Application
    Filed: December 20, 2016
    Publication date: April 13, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yusuke KOBAYASHI, Yoshihisa IWATA, Takeshi SUGIMOTO
  • Patent number: 9576968
    Abstract: A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction.
    Type: Grant
    Filed: June 1, 2015
    Date of Patent: February 21, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tomoo Hishida, Yoshihisa Iwata
  • Patent number: 9553132
    Abstract: According to the embodiment, a semiconductor memory device includes a first conductive layer, a second conductive layer, a first memory cell, a second memory cell, a third conductive layer, a first contact, a intermediate memory cell, a fourth conductive layer, a third memory cell, a fifth conductive layer, and a second contact. The third conductive layer is separated from the first conductive layer and the second conductive layer in a third direction crossing a first direction and crossing a second direction and extends in the second direction. The fifth conductive layer is separated from the second conductive layer in the third direction and extends in the second direction. A first length of the second conductive layer along the second direction is shorter than a second length of the fifth conductive layer along the second direction.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: January 24, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yusuke Kobayashi, Yoshihisa Iwata, Takeshi Sugimoto
  • Publication number: 20160307838
    Abstract: In a nonvolatile semiconductor memory device, a stacked body is formed by alternately stacking dielectric films and conductive films on a silicon substrate and a plurality of through holes extending in the stacking direction are formed in a matrix configuration. A shunt interconnect and a bit interconnect are provided above the stacked body. Conductor pillars are buried inside the through holes arranged in a line immediately below the shunt interconnect out of the plurality of through holes, and semiconductor pillars are buried inside the remaining through holes. The conductive pillars are formed from a metal, or low resistance silicon. Its upper end portion is connected to the shunt interconnect and its lower end portion is connected to a cell source formed in an upper layer portion of the silicon substrate.
    Type: Application
    Filed: June 23, 2016
    Publication date: October 20, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takashi MAEDA, Yoshihisa IWATA
  • Publication number: 20160267955
    Abstract: A memory device according to one embodiment includes a magnetic wire; a conductive first line which faces one of opposite ends of the magnetic wire at a distance; and a conductive second line which faces the other of the opposite ends of the magnetic wire at a distance. A voltage applied to the first line is changed in a positive direction and a second voltage applied to the second line is changed in a negative direction to form a potential difference in the magnetic wire.
    Type: Application
    Filed: August 5, 2015
    Publication date: September 15, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Yoshihisa IWATA
  • Publication number: 20160267974
    Abstract: A semiconductor storage device includes a variable resistive element, which changes a resistance value according to a polarity and a magnitude of an applied voltage, as a memory element. The semiconductor storage device includes a standby mode in which a power source voltage or a ground voltage is applied to both of a word line and a bit line. The semiconductor storage device includes a data write mode in which a voltage difference equal to or more than a first voltage is applied between the word line and the bit line. The semiconductor storage device includes a read mode in which a voltage difference smaller than the first voltage is applied between the word line and the bit line by changing only one voltage of the word line and the bit line which is applied in the standby mode, and data written in the memory element is read.
    Type: Application
    Filed: August 25, 2015
    Publication date: September 15, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takayuki MIYAZAKI, Reika ICHIHARA, Kikuko SUGIMAE, Yoshihisa IWATA
  • Patent number: 9424919
    Abstract: According to one embodiment, provided is a semiconductor storage device that includes a control circuit to control the voltage that is applied to the memory cell. The control circuit is configured to execute a reset operation that applies a reset voltage of a first polarity to a selected memory cell that is connected to a selected first wire and a selected second wire during a reset operation. The control circuit is configured to execute a cancel operation that applies a cancel voltage of a second polarity that is opposite to the first polarity to an unselected memory cell and at the same time can execute a verify operation that reads out the state of the selected memory cell by applying a readout voltage of the second polarity to the selected memory cell. The cancel voltage and the readout voltage are the same voltage value.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: August 23, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Reika Ichihara, Kikuko Sugimae, Takayuki Miyazaki, Yoshihisa Iwata
  • Patent number: 9412756
    Abstract: In a nonvolatile semiconductor memory device, a stacked body is formed by alternately stacking dielectric films and conductive films on a silicon substrate and a plurality of through holes extending in the stacking direction are formed in a matrix configuration. A shunt interconnect and a bit interconnect are provided above the stacked body. Conductor pillars are buried inside the through holes arranged in a line immediately below the shunt interconnect out of the plurality of through holes, and semiconductor pillars are buried inside the remaining through holes. The conductive pillars are formed from a metal, or low resistance silicon. Its upper end portion is connected to the shunt interconnect and its lower end portion is connected to a cell source formed in an upper layer portion of the silicon substrate.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: August 9, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takashi Maeda, Yoshihisa Iwata
  • Patent number: RE46949
    Abstract: Memory strings includes: a first semiconductor layer including a columnar portion extending in a direction perpendicular to a substrate; a first electric charge storage layer formed to surround a side surface of the columnar portion; and a first conductive layer formed to surround the first electric charge storage layer. First selection transistors includes: a second semiconductor layer extending upward from a top surface of the columnar portion; a second electric charge storage layer formed to surround a side surface of the second semiconductor layer; and a second conductive layer formed to surround the second electric charge storage layer. The non-volatile semiconductor storage device further includes a control circuit that causes, prior to reading data from a selected one of the memory strings, electric charges to be accumulated in the second electric charge storage layer of one of the first selection transistors connected to an unselected one of the memory strings.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: July 10, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takashi Maeda, Yoshihisa Iwata