Patents by Inventor Yoshihisa Kagawa
Yoshihisa Kagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10930845Abstract: A memory device includes: a memory layer that is isolated for each memory cell and stores information by a variation of a resistance value; an ion source layer that is formed to be isolated for each memory cell and to be laminated on the memory layer, and contains at least one kind of element selected from Cu, Ag, Zn, Al and Zr and at least one kind of element selected from Te, S and Se; an insulation layer that isolates the memory layer and the ion source layer for each memory cell; and a diffusion preventing barrier that is provided at a periphery of the memory layer and the ion source layer of each memory cell to prevent the diffusion of the element.Type: GrantFiled: April 18, 2019Date of Patent: February 23, 2021Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventor: Yoshihisa Kagawa
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Patent number: 10837448Abstract: A counter-rotating axial flow fan includes a first fan including a first impeller including first blades radially arranged around a predetermined central axis, a first motor rotating the first impeller around the central axis, and a first case surrounding an outer periphery of the first impeller, and a second fan including a second impeller including second blades radially arranged around the central axis, a second motor rotating the second impeller around the central axis, and a second case surrounding an outer periphery of the second impeller. End surfaces of the first and second cases contact each other at a first position in an axial direction, the first and second motors face in opposite directions from each other in the axial direction, and end surfaces of the first and second motors are opposite to each other at a second position that differs from the first position.Type: GrantFiled: March 15, 2019Date of Patent: November 17, 2020Assignee: NIDEC SERVO CORPORATIONInventors: Yoshihiko Kato, Takahiro Bamba, Yoshihisa Kagawa, Takanori Abe
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Patent number: 10804313Abstract: The present technology relates to a semiconductor device and a solid-state imaging device of which crack resistance can be improved in a simpler way. The semiconductor device has an upper substrate that is constituted by a Si substrate and wiring layers laminated on the Si substrate and a second substrate that is constituted by a Si substrate and wiring layers laminated on the Si substrate and is joined to the upper substrate. In addition, a pad for wire bonding or probing is formed in the upper substrate, and pads for protecting corner or side parts of the pad for wire bonding or probing are radially laminated and provided in each of the wiring layers between the pad and the Si substrate of the lower substrate. The present technology can be applied to a solid-state imaging device.Type: GrantFiled: June 6, 2018Date of Patent: October 13, 2020Assignee: Sony CorporationInventors: Yoshihisa Kagawa, Nobutoshi Fujii, Masanaga Fukasawa, Tokihisa Kaneguchi, Yoshiya Hagimoto, Kenichi Aoyagi, Ikue Mitsuhashi
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Patent number: 10707258Abstract: A semiconductor device includes a first substrate having an attaching surface on which first electrodes and a first insulating film are exposed, an insulating thin film that covers the attaching surface of the first substrate, and a second substrate which has an attaching surface on which second electrodes and a second insulating film are exposed and is attached to the first substrate in a state in which the attaching surface of the second substrate and the attaching surface of the first substrate are attached together sandwiching the insulating thin film therebetween, and the first electrodes and the second electrodes deform and break a part of the insulating thin film so as to be directly electrically connected to each other.Type: GrantFiled: May 23, 2018Date of Patent: July 7, 2020Assignee: Sony CorporationInventors: Nobutoshi Fujii, Yoshiya Hagimoto, Kenichi Aoyagi, Yoshihisa Kagawa
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Publication number: 20200185433Abstract: The present technology relates to a semiconductor device, a solid-state image pickup element, an imaging device, and an electronic apparatus that can suppress characteristic fluctuations caused by capacitance fluctuations due to a dummy wire, while maintaining an affixing bonding strength by the dummy wire. Two or more chips in which wires that are electrically connected are formed on bonding surfaces and the bonding surfaces opposing each other are bonded to be laminated are included and, with respect to a region where the wires are periodically and repeatedly disposed in sharing units each made up of a plurality of pixels sharing the same floating diffusion contact, a dummy wire is disposed at the center position thereof on the bonding surface at a pitch of the sharing unit. The present technology can be applied to a CMOS image sensor.Type: ApplicationFiled: February 19, 2020Publication date: June 11, 2020Applicant: SONY CORPORATIONInventors: Rena SUZUKI, Takeshi MATSUNUMA, Naoki JYO, Yoshihisa KAGAWA
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Patent number: 10665623Abstract: The present technology relates to a semiconductor device, a solid-state image pickup element, an imaging device, and an electronic apparatus that can suppress characteristic fluctuations caused by capacitance fluctuations due to a dummy wire, while maintaining an affixing bonding strength by the dummy wire. Two or more chips in which wires that are electrically connected are formed on bonding surfaces and the bonding surfaces opposing each other are bonded to be laminated are included and, with respect to a region where the wires are periodically and repeatedly disposed in sharing units each made up of a plurality of pixels sharing the same floating diffusion contact, a dummy wire is disposed at the center position thereof on the bonding surface at a pitch of the sharing unit. The present technology can be applied to a CMOS image sensor.Type: GrantFiled: February 12, 2016Date of Patent: May 26, 2020Assignee: SONY CORPORATIONInventors: Rena Suzuki, Takeshi Matsunuma, Naoki Jyo, Yoshihisa Kagawa
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Publication number: 20190386056Abstract: A semiconductor device includes a first substrate having an attaching surface on which first electrodes and a first insulating film are exposed, an insulating thin film that covers the attaching surface of the first substrate, and a second substrate which has an attaching surface on which second electrodes and a second insulating film are exposed and is attached to the first substrate in a state in which the attaching surface of the second substrate and the attaching surface of the first substrate are attached together sandwiching the insulating thin film therebetween, and the first electrodes and the second electrodes deform and break a part of the insulating thin film so as to be directly electrically connected to each other.Type: ApplicationFiled: August 28, 2019Publication date: December 19, 2019Applicant: Sony CorporationInventors: Nobutoshi Fujii, Yoshiya Hagimoto, Kenichi Aoyagi, Yoshihisa Kagawa
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Publication number: 20190301472Abstract: A counter-rotating fan includes a first fan including a first impeller including first blades radially arranged around a predetermined center axis, a first motor that rotates the first impeller around the center axis, and a first case surrounding an outer circumference of the first impeller, and a second fan including a second impeller including second blades radially arranged around the center axis, a second motor that rotates the second impeller around the center axis, and a second case surrounding an outer circumference of the second impeller. The first blades include a front edge located foremost in a rotation direction and a rear edge located rearmost in the rotation direction. A radially outermost end of the rear edge is located closer to the second fan than a radially innermost end.Type: ApplicationFiled: February 12, 2019Publication date: October 3, 2019Inventors: Yoshihiko KATO, Takahiro BAMBA, Yoshihisa KAGAWA, Takanori ABE
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Publication number: 20190301473Abstract: A counter-rotating axial flow fan includes a first fan including a first impeller including first blades radially arranged around a predetermined central axis, a first motor rotating the first impeller around the central axis, and a first case surrounding an outer periphery of the first impeller, and a second fan including a second impeller including second blades radially arranged around the central axis, a second motor rotating the second impeller around the central axis, and a second case surrounding an outer periphery of the second impeller. End surfaces of the first and second cases contact each other at a first position in an axial direction, the first and second motors face in opposite directions from each other in the axial direction, and end surfaces of the first and second motors are opposite to each other at a second position that differs from the first position.Type: ApplicationFiled: March 15, 2019Publication date: October 3, 2019Inventors: Yoshihiko KATO, Takahiro BAMBA, Yoshihisa KAGAWA, Takanori ABE
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Patent number: 10431621Abstract: Disclosed herein is a semiconductor device, including: a first substrate including a first electrode, and a first insulating film configured from a diffusion preventing material for the first electrode and covering a periphery of the first electrode, the first electrode and the first insulating film cooperating with each other to configure a bonding face; and a second substrate bonded to and provided on the first substrate and including a second electrode joined to the first electrode, and a second insulating film configured from a diffusion preventing material for the second electrode and covering a periphery of the second electrode, the second electrode and the second insulating film cooperating with each other to configure a bonding face to the first substrate.Type: GrantFiled: May 30, 2018Date of Patent: October 1, 2019Assignee: Sony CorporationInventors: Yoshihisa Kagawa, Kenichi Aoyagi, Yoshiya Hagimoto, Nobutoshi Fujii
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Publication number: 20190273109Abstract: Disclosed herein is a semiconductor device, including: a first substrate including a first electrode, and a first insulating film configured from a diffusion preventing material for the first electrode and covering a periphery of the first electrode, the first electrode and the first insulating film cooperating with each other to configure a bonding face; and a second substrate bonded to and provided on the first substrate and including a second electrode joined to the first electrode, and a second insulating film configured from a diffusion preventing material for the second electrode and covering a periphery of the second electrode, the second electrode and the second insulating film cooperating with each other to configure a bonding face to the first substrate.Type: ApplicationFiled: May 13, 2019Publication date: September 5, 2019Applicant: Sony CorporationInventors: Yoshihisa Kagawa, Kenichi Aoyagi, Yoshiya Hagimoto, Nobutoshi Fujii
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Publication number: 20190252604Abstract: A memory device includes: a memory layer that is isolated for each memory cell and stores information by a variation of a resistance value; an ion source layer that is formed to be isolated for each memory cell and to be laminated on the memory layer, and contains at least one kind of element selected from Cu, Ag, Zn, Al and Zr and at least one kind of element selected from Te, S and Se; an insulation layer that isolates the memory layer and the ion source layer for each memory cell; and a diffusion preventing barrier that is provided at a periphery of the memory layer and the ion source layer of each memory cell to prevent the diffusion of the element.Type: ApplicationFiled: April 18, 2019Publication date: August 15, 2019Applicant: Sony Semiconductor Solutions CorporationInventor: Yoshihisa Kagawa
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Patent number: 10347832Abstract: A memory device includes: a memory layer that is isolated for each memory cell and stores information by a variation of a resistance value; an ion source layer that is formed to be isolated for each memory cell and to be laminated on the memory layer, and contains at least one kind of element selected from Cu, Ag, Zn, Al and Zr and at least one kind of element selected from Te, S and Se; an insulation layer that isolates the memory layer and the ion source layer for each memory cell; and a diffusion preventing barrier that is provided at a periphery of the memory layer and the ion source layer of each memory cell to prevent the diffusion of the element.Type: GrantFiled: July 18, 2017Date of Patent: July 9, 2019Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventor: Yoshihisa Kagawa
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Patent number: 10236238Abstract: A first semiconductor device includes: a first wiring layer including a first interlayer insulating film, a first electrode pad, and a first dummy electrode, the first electrode pad being embedded in the first interlayer insulating film and having one surface located on same plane as one surface of the first interlayer insulating film, and the first dummy electrode being embedded in the first interlayer insulating film, having one surface located on same plane as the one surface of the first interlayer insulating film, and being disposed around the first electrode pad; and a second wiring layer including a second interlayer insulating film, a second electrode pad, and a second dummy electrode, the second electrode pad being embedded in the second interlayer insulating film, having one surface located on same surface as one surface of the second interlayer insulating film, and being bonded to the first electrode pad, and the second dummy electrode having one surface located on same plane as the surface locatedType: GrantFiled: September 21, 2017Date of Patent: March 19, 2019Assignee: Sony CorporationInventors: Nobutoshi Fujii, Yoshihisa Kagawa
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Patent number: 10134795Abstract: A semiconductor device includes a first substrate having an attaching surface on which first electrodes and a first insulating film are exposed, an insulating thin film that covers the attaching surface of the first substrate, and a second substrate which has an attaching surface on which second electrodes and a second insulating film are exposed and is attached to the first substrate in a state in which the attaching surface of the second substrate and the attaching surface of the first substrate are attached together sandwiching the insulating thin film therebetween, and the first electrodes and the second electrodes deform and break a part of the insulating thin film so as to be directly electrically connected to each other.Type: GrantFiled: May 30, 2017Date of Patent: November 20, 2018Assignee: Sony CorporationInventors: Nobutoshi Fujii, Yoshiya Hagimoto, Kenichi Aoyagi, Yoshihisa Kagawa
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Publication number: 20180286911Abstract: The present technology relates to a semiconductor device and a solid-state imaging device of which crack resistance can be improved in a simpler way. The semiconductor device has an upper substrate that is constituted by a Si substrate and wiring layers laminated on the Si substrate and a second substrate that is constituted by a Si substrate and wiring layers laminated on the Si substrate and is joined to the upper substrate. In addition, a pad for wire bonding or probing is formed in the upper substrate, and pads for protecting corner or side parts of the pad for wire bonding or probing are radially laminated and provided in each of the wiring layers between the pad and the Si substrate of the lower substrate. The present technology can be applied to a solid-state imaging device.Type: ApplicationFiled: June 6, 2018Publication date: October 4, 2018Applicant: Sony CorporationInventors: Yoshihisa KAGAWA, Nobutoshi FUJII, Masanaga FUKASAWA, Tokihisa KANEGUCHI, Yoshiya HAGIMOTO, Kenichi AOYAGI, Ikue MITSUHASHI
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Publication number: 20180277585Abstract: Disclosed herein is a semiconductor device, including: a first substrate including a first electrode, and a first insulating film configured from a diffusion preventing material for the first electrode and covering a periphery of the first electrode, the first electrode and the first insulating film cooperating with each other to configure a bonding face; and a second substrate bonded to and provided on the first substrate and including a second electrode joined to the first electrode, and a second insulating film configured from a diffusion preventing material for the second electrode and covering a periphery of the second electrode, the second electrode and the second insulating film cooperating with each other to configure a bonding face to the first substrate.Type: ApplicationFiled: May 30, 2018Publication date: September 27, 2018Inventors: Yoshihisa Kagawa, Kenichi Aoyagi, Yoshiya Hagimoto, Nobutoshi Fujii
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Publication number: 20180269248Abstract: A semiconductor device includes a first substrate having an attaching surface on which first electrodes and a first insulating film are exposed, an insulating thin film that covers the attaching surface of the first substrate, and a second substrate which has an attaching surface on which second electrodes and a second insulating film are exposed and is attached to the first substrate in a state in which the attaching surface of the second substrate and the attaching surface of the first substrate are attached together sandwiching the insulating thin film therebetween, and the first electrodes and the second electrodes deform and break a part of the insulating thin film so as to be directly electrically connected to each other.Type: ApplicationFiled: May 23, 2018Publication date: September 20, 2018Applicant: Sony CorporationInventors: Nobutoshi Fujii, Yoshiya Hagimoto, Kenichi Aoyagi, Yoshihisa Kagawa
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Publication number: 20180233435Abstract: A first semiconductor device includes: a first wiring layer including a first interlayer insulating film, a first electrode pad, and a first dummy electrode, the first electrode pad being embedded in the first interlayer insulating film and having one surface located on same plane as one surface of the first interlayer insulating film, and the first dummy electrode being embedded in the first interlayer insulating film, having one surface located on same plane as the one surface of the first interlayer insulating film, and being disposed around the first electrode pad; and a second wiring layer including a second interlayer insulating film, a second electrode pad, and a second dummy electrode, the second electrode pad being embedded in the second interlayer insulating film, having one surface located on same surface as one surface of the second interlayer insulating film, and being bonded to the first electrode pad, and the second dummy electrode having one surface located on same plane as the surface locatedType: ApplicationFiled: April 4, 2018Publication date: August 16, 2018Inventors: Nobutoshi Fujii, Yoshihisa Kagawa
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Patent number: 10038024Abstract: Disclosed herein is a semiconductor device, including: a first substrate including a first electrode, and a first insulating film configured from a diffusion preventing material for the first electrode and covering a periphery of the first electrode, the first electrode and the first insulating film cooperating with each other to configure a bonding face; and a second substrate bonded to and provided on the first substrate and including a second electrode joined to the first electrode, and a second insulating film configured from a diffusion preventing material for the second electrode and covering a periphery of the second electrode, the second electrode and the second insulating film cooperating with each other to configure a bonding face to the first substrate.Type: GrantFiled: August 4, 2016Date of Patent: July 31, 2018Assignee: Sony CorporationInventors: Yoshihisa Kagawa, Kenichi Aoyagi, Yoshiya Hagimoto, Nobutoshi Fujii