Patents by Inventor Yoshihisa Kagawa

Yoshihisa Kagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10930845
    Abstract: A memory device includes: a memory layer that is isolated for each memory cell and stores information by a variation of a resistance value; an ion source layer that is formed to be isolated for each memory cell and to be laminated on the memory layer, and contains at least one kind of element selected from Cu, Ag, Zn, Al and Zr and at least one kind of element selected from Te, S and Se; an insulation layer that isolates the memory layer and the ion source layer for each memory cell; and a diffusion preventing barrier that is provided at a periphery of the memory layer and the ion source layer of each memory cell to prevent the diffusion of the element.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: February 23, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Yoshihisa Kagawa
  • Patent number: 10837448
    Abstract: A counter-rotating axial flow fan includes a first fan including a first impeller including first blades radially arranged around a predetermined central axis, a first motor rotating the first impeller around the central axis, and a first case surrounding an outer periphery of the first impeller, and a second fan including a second impeller including second blades radially arranged around the central axis, a second motor rotating the second impeller around the central axis, and a second case surrounding an outer periphery of the second impeller. End surfaces of the first and second cases contact each other at a first position in an axial direction, the first and second motors face in opposite directions from each other in the axial direction, and end surfaces of the first and second motors are opposite to each other at a second position that differs from the first position.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: November 17, 2020
    Assignee: NIDEC SERVO CORPORATION
    Inventors: Yoshihiko Kato, Takahiro Bamba, Yoshihisa Kagawa, Takanori Abe
  • Patent number: 10804313
    Abstract: The present technology relates to a semiconductor device and a solid-state imaging device of which crack resistance can be improved in a simpler way. The semiconductor device has an upper substrate that is constituted by a Si substrate and wiring layers laminated on the Si substrate and a second substrate that is constituted by a Si substrate and wiring layers laminated on the Si substrate and is joined to the upper substrate. In addition, a pad for wire bonding or probing is formed in the upper substrate, and pads for protecting corner or side parts of the pad for wire bonding or probing are radially laminated and provided in each of the wiring layers between the pad and the Si substrate of the lower substrate. The present technology can be applied to a solid-state imaging device.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: October 13, 2020
    Assignee: Sony Corporation
    Inventors: Yoshihisa Kagawa, Nobutoshi Fujii, Masanaga Fukasawa, Tokihisa Kaneguchi, Yoshiya Hagimoto, Kenichi Aoyagi, Ikue Mitsuhashi
  • Patent number: 10707258
    Abstract: A semiconductor device includes a first substrate having an attaching surface on which first electrodes and a first insulating film are exposed, an insulating thin film that covers the attaching surface of the first substrate, and a second substrate which has an attaching surface on which second electrodes and a second insulating film are exposed and is attached to the first substrate in a state in which the attaching surface of the second substrate and the attaching surface of the first substrate are attached together sandwiching the insulating thin film therebetween, and the first electrodes and the second electrodes deform and break a part of the insulating thin film so as to be directly electrically connected to each other.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: July 7, 2020
    Assignee: Sony Corporation
    Inventors: Nobutoshi Fujii, Yoshiya Hagimoto, Kenichi Aoyagi, Yoshihisa Kagawa
  • Publication number: 20200185433
    Abstract: The present technology relates to a semiconductor device, a solid-state image pickup element, an imaging device, and an electronic apparatus that can suppress characteristic fluctuations caused by capacitance fluctuations due to a dummy wire, while maintaining an affixing bonding strength by the dummy wire. Two or more chips in which wires that are electrically connected are formed on bonding surfaces and the bonding surfaces opposing each other are bonded to be laminated are included and, with respect to a region where the wires are periodically and repeatedly disposed in sharing units each made up of a plurality of pixels sharing the same floating diffusion contact, a dummy wire is disposed at the center position thereof on the bonding surface at a pitch of the sharing unit. The present technology can be applied to a CMOS image sensor.
    Type: Application
    Filed: February 19, 2020
    Publication date: June 11, 2020
    Applicant: SONY CORPORATION
    Inventors: Rena SUZUKI, Takeshi MATSUNUMA, Naoki JYO, Yoshihisa KAGAWA
  • Patent number: 10665623
    Abstract: The present technology relates to a semiconductor device, a solid-state image pickup element, an imaging device, and an electronic apparatus that can suppress characteristic fluctuations caused by capacitance fluctuations due to a dummy wire, while maintaining an affixing bonding strength by the dummy wire. Two or more chips in which wires that are electrically connected are formed on bonding surfaces and the bonding surfaces opposing each other are bonded to be laminated are included and, with respect to a region where the wires are periodically and repeatedly disposed in sharing units each made up of a plurality of pixels sharing the same floating diffusion contact, a dummy wire is disposed at the center position thereof on the bonding surface at a pitch of the sharing unit. The present technology can be applied to a CMOS image sensor.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: May 26, 2020
    Assignee: SONY CORPORATION
    Inventors: Rena Suzuki, Takeshi Matsunuma, Naoki Jyo, Yoshihisa Kagawa
  • Publication number: 20190386056
    Abstract: A semiconductor device includes a first substrate having an attaching surface on which first electrodes and a first insulating film are exposed, an insulating thin film that covers the attaching surface of the first substrate, and a second substrate which has an attaching surface on which second electrodes and a second insulating film are exposed and is attached to the first substrate in a state in which the attaching surface of the second substrate and the attaching surface of the first substrate are attached together sandwiching the insulating thin film therebetween, and the first electrodes and the second electrodes deform and break a part of the insulating thin film so as to be directly electrically connected to each other.
    Type: Application
    Filed: August 28, 2019
    Publication date: December 19, 2019
    Applicant: Sony Corporation
    Inventors: Nobutoshi Fujii, Yoshiya Hagimoto, Kenichi Aoyagi, Yoshihisa Kagawa
  • Publication number: 20190301472
    Abstract: A counter-rotating fan includes a first fan including a first impeller including first blades radially arranged around a predetermined center axis, a first motor that rotates the first impeller around the center axis, and a first case surrounding an outer circumference of the first impeller, and a second fan including a second impeller including second blades radially arranged around the center axis, a second motor that rotates the second impeller around the center axis, and a second case surrounding an outer circumference of the second impeller. The first blades include a front edge located foremost in a rotation direction and a rear edge located rearmost in the rotation direction. A radially outermost end of the rear edge is located closer to the second fan than a radially innermost end.
    Type: Application
    Filed: February 12, 2019
    Publication date: October 3, 2019
    Inventors: Yoshihiko KATO, Takahiro BAMBA, Yoshihisa KAGAWA, Takanori ABE
  • Publication number: 20190301473
    Abstract: A counter-rotating axial flow fan includes a first fan including a first impeller including first blades radially arranged around a predetermined central axis, a first motor rotating the first impeller around the central axis, and a first case surrounding an outer periphery of the first impeller, and a second fan including a second impeller including second blades radially arranged around the central axis, a second motor rotating the second impeller around the central axis, and a second case surrounding an outer periphery of the second impeller. End surfaces of the first and second cases contact each other at a first position in an axial direction, the first and second motors face in opposite directions from each other in the axial direction, and end surfaces of the first and second motors are opposite to each other at a second position that differs from the first position.
    Type: Application
    Filed: March 15, 2019
    Publication date: October 3, 2019
    Inventors: Yoshihiko KATO, Takahiro BAMBA, Yoshihisa KAGAWA, Takanori ABE
  • Patent number: 10431621
    Abstract: Disclosed herein is a semiconductor device, including: a first substrate including a first electrode, and a first insulating film configured from a diffusion preventing material for the first electrode and covering a periphery of the first electrode, the first electrode and the first insulating film cooperating with each other to configure a bonding face; and a second substrate bonded to and provided on the first substrate and including a second electrode joined to the first electrode, and a second insulating film configured from a diffusion preventing material for the second electrode and covering a periphery of the second electrode, the second electrode and the second insulating film cooperating with each other to configure a bonding face to the first substrate.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: October 1, 2019
    Assignee: Sony Corporation
    Inventors: Yoshihisa Kagawa, Kenichi Aoyagi, Yoshiya Hagimoto, Nobutoshi Fujii
  • Publication number: 20190273109
    Abstract: Disclosed herein is a semiconductor device, including: a first substrate including a first electrode, and a first insulating film configured from a diffusion preventing material for the first electrode and covering a periphery of the first electrode, the first electrode and the first insulating film cooperating with each other to configure a bonding face; and a second substrate bonded to and provided on the first substrate and including a second electrode joined to the first electrode, and a second insulating film configured from a diffusion preventing material for the second electrode and covering a periphery of the second electrode, the second electrode and the second insulating film cooperating with each other to configure a bonding face to the first substrate.
    Type: Application
    Filed: May 13, 2019
    Publication date: September 5, 2019
    Applicant: Sony Corporation
    Inventors: Yoshihisa Kagawa, Kenichi Aoyagi, Yoshiya Hagimoto, Nobutoshi Fujii
  • Publication number: 20190252604
    Abstract: A memory device includes: a memory layer that is isolated for each memory cell and stores information by a variation of a resistance value; an ion source layer that is formed to be isolated for each memory cell and to be laminated on the memory layer, and contains at least one kind of element selected from Cu, Ag, Zn, Al and Zr and at least one kind of element selected from Te, S and Se; an insulation layer that isolates the memory layer and the ion source layer for each memory cell; and a diffusion preventing barrier that is provided at a periphery of the memory layer and the ion source layer of each memory cell to prevent the diffusion of the element.
    Type: Application
    Filed: April 18, 2019
    Publication date: August 15, 2019
    Applicant: Sony Semiconductor Solutions Corporation
    Inventor: Yoshihisa Kagawa
  • Patent number: 10347832
    Abstract: A memory device includes: a memory layer that is isolated for each memory cell and stores information by a variation of a resistance value; an ion source layer that is formed to be isolated for each memory cell and to be laminated on the memory layer, and contains at least one kind of element selected from Cu, Ag, Zn, Al and Zr and at least one kind of element selected from Te, S and Se; an insulation layer that isolates the memory layer and the ion source layer for each memory cell; and a diffusion preventing barrier that is provided at a periphery of the memory layer and the ion source layer of each memory cell to prevent the diffusion of the element.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: July 9, 2019
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Yoshihisa Kagawa
  • Patent number: 10236238
    Abstract: A first semiconductor device includes: a first wiring layer including a first interlayer insulating film, a first electrode pad, and a first dummy electrode, the first electrode pad being embedded in the first interlayer insulating film and having one surface located on same plane as one surface of the first interlayer insulating film, and the first dummy electrode being embedded in the first interlayer insulating film, having one surface located on same plane as the one surface of the first interlayer insulating film, and being disposed around the first electrode pad; and a second wiring layer including a second interlayer insulating film, a second electrode pad, and a second dummy electrode, the second electrode pad being embedded in the second interlayer insulating film, having one surface located on same surface as one surface of the second interlayer insulating film, and being bonded to the first electrode pad, and the second dummy electrode having one surface located on same plane as the surface located
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: March 19, 2019
    Assignee: Sony Corporation
    Inventors: Nobutoshi Fujii, Yoshihisa Kagawa
  • Patent number: 10134795
    Abstract: A semiconductor device includes a first substrate having an attaching surface on which first electrodes and a first insulating film are exposed, an insulating thin film that covers the attaching surface of the first substrate, and a second substrate which has an attaching surface on which second electrodes and a second insulating film are exposed and is attached to the first substrate in a state in which the attaching surface of the second substrate and the attaching surface of the first substrate are attached together sandwiching the insulating thin film therebetween, and the first electrodes and the second electrodes deform and break a part of the insulating thin film so as to be directly electrically connected to each other.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: November 20, 2018
    Assignee: Sony Corporation
    Inventors: Nobutoshi Fujii, Yoshiya Hagimoto, Kenichi Aoyagi, Yoshihisa Kagawa
  • Publication number: 20180286911
    Abstract: The present technology relates to a semiconductor device and a solid-state imaging device of which crack resistance can be improved in a simpler way. The semiconductor device has an upper substrate that is constituted by a Si substrate and wiring layers laminated on the Si substrate and a second substrate that is constituted by a Si substrate and wiring layers laminated on the Si substrate and is joined to the upper substrate. In addition, a pad for wire bonding or probing is formed in the upper substrate, and pads for protecting corner or side parts of the pad for wire bonding or probing are radially laminated and provided in each of the wiring layers between the pad and the Si substrate of the lower substrate. The present technology can be applied to a solid-state imaging device.
    Type: Application
    Filed: June 6, 2018
    Publication date: October 4, 2018
    Applicant: Sony Corporation
    Inventors: Yoshihisa KAGAWA, Nobutoshi FUJII, Masanaga FUKASAWA, Tokihisa KANEGUCHI, Yoshiya HAGIMOTO, Kenichi AOYAGI, Ikue MITSUHASHI
  • Publication number: 20180277585
    Abstract: Disclosed herein is a semiconductor device, including: a first substrate including a first electrode, and a first insulating film configured from a diffusion preventing material for the first electrode and covering a periphery of the first electrode, the first electrode and the first insulating film cooperating with each other to configure a bonding face; and a second substrate bonded to and provided on the first substrate and including a second electrode joined to the first electrode, and a second insulating film configured from a diffusion preventing material for the second electrode and covering a periphery of the second electrode, the second electrode and the second insulating film cooperating with each other to configure a bonding face to the first substrate.
    Type: Application
    Filed: May 30, 2018
    Publication date: September 27, 2018
    Inventors: Yoshihisa Kagawa, Kenichi Aoyagi, Yoshiya Hagimoto, Nobutoshi Fujii
  • Publication number: 20180269248
    Abstract: A semiconductor device includes a first substrate having an attaching surface on which first electrodes and a first insulating film are exposed, an insulating thin film that covers the attaching surface of the first substrate, and a second substrate which has an attaching surface on which second electrodes and a second insulating film are exposed and is attached to the first substrate in a state in which the attaching surface of the second substrate and the attaching surface of the first substrate are attached together sandwiching the insulating thin film therebetween, and the first electrodes and the second electrodes deform and break a part of the insulating thin film so as to be directly electrically connected to each other.
    Type: Application
    Filed: May 23, 2018
    Publication date: September 20, 2018
    Applicant: Sony Corporation
    Inventors: Nobutoshi Fujii, Yoshiya Hagimoto, Kenichi Aoyagi, Yoshihisa Kagawa
  • Publication number: 20180233435
    Abstract: A first semiconductor device includes: a first wiring layer including a first interlayer insulating film, a first electrode pad, and a first dummy electrode, the first electrode pad being embedded in the first interlayer insulating film and having one surface located on same plane as one surface of the first interlayer insulating film, and the first dummy electrode being embedded in the first interlayer insulating film, having one surface located on same plane as the one surface of the first interlayer insulating film, and being disposed around the first electrode pad; and a second wiring layer including a second interlayer insulating film, a second electrode pad, and a second dummy electrode, the second electrode pad being embedded in the second interlayer insulating film, having one surface located on same surface as one surface of the second interlayer insulating film, and being bonded to the first electrode pad, and the second dummy electrode having one surface located on same plane as the surface located
    Type: Application
    Filed: April 4, 2018
    Publication date: August 16, 2018
    Inventors: Nobutoshi Fujii, Yoshihisa Kagawa
  • Patent number: 10038024
    Abstract: Disclosed herein is a semiconductor device, including: a first substrate including a first electrode, and a first insulating film configured from a diffusion preventing material for the first electrode and covering a periphery of the first electrode, the first electrode and the first insulating film cooperating with each other to configure a bonding face; and a second substrate bonded to and provided on the first substrate and including a second electrode joined to the first electrode, and a second insulating film configured from a diffusion preventing material for the second electrode and covering a periphery of the second electrode, the second electrode and the second insulating film cooperating with each other to configure a bonding face to the first substrate.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: July 31, 2018
    Assignee: Sony Corporation
    Inventors: Yoshihisa Kagawa, Kenichi Aoyagi, Yoshiya Hagimoto, Nobutoshi Fujii