Patents by Inventor Yoshihisa Kagawa
Yoshihisa Kagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11923279Abstract: A first semiconductor device includes: a first wiring layer including a first interlayer insulating film, a first electrode pad, and a first dummy electrode, the first electrode pad being embedded in the first interlayer insulating film and having one surface located on same plane as one surface of the first interlayer insulating film, and the first dummy electrode being embedded in the first interlayer insulating film, having one surface located on same plane as the one surface of the first interlayer insulating film, and being disposed around the first electrode pad; and a second wiring layer including a second interlayer insulating film, a second electrode pad, and a second dummy electrode, the second electrode pad being embedded in the second interlayer insulating film, having one surface located on same surface as one surface of the second interlayer insulating film, and being bonded to the first electrode pad, and the second dummy electrode having one surface located on same plane as the surface locatedType: GrantFiled: December 7, 2022Date of Patent: March 5, 2024Assignee: SONY GROUP CORPORATIONInventors: Nobutoshi Fujii, Yoshihisa Kagawa
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Publication number: 20230361047Abstract: A semiconductor device according to an embodiment of the present disclosure includes: a first substrate including a first junction portion; and a second substrate including a second junction portion. The second junction portion is joined to the first junction portion. The first substrate further includes a first multilayer wiring layer in which one surface of a first wiring line faces a first insulating layer and another surface opposed to the one surface is in contact with a second insulating layer. The first multilayer wiring layer is electrically coupled to the first junction portion via the first insulating layer. The first wiring line is formed closest to a junction surface with the second substrate. The second insulating layer has a lower relative dielectric constant than a relative dielectric constant of the first insulating layer.Type: ApplicationFiled: July 13, 2023Publication date: November 9, 2023Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Hiroyuki KAWASHIMA, Ryoichi NAKAMURA, Yoshihisa KAGAWA, Yuusaku KOBAYASHI
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Publication number: 20230282666Abstract: An imaging device according to an embodiment of the present disclosure includes: a first wiring layer; a first insulating film; and a second insulating film. The first wiring layer includes a plurality of first wiring lines that extends in one direction. The plurality of first wiring lines each has a notch at at least one of ends of one surface in a cross section orthogonal to an extending direction. The first insulating film covers a surface of the first wiring layer. The second insulating film is stacked on the first insulating film. The second insulating film forms a gap between the plurality of adjacent first wiring lines.Type: ApplicationFiled: July 8, 2021Publication date: September 7, 2023Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Yoshihisa KAGAWA, Hiroshi HORIKOSHI, Masaki HANEDA, Hiroshi NAKAZAWA, Takatoshi KAMESHIMA
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Patent number: 11749609Abstract: A semiconductor device according to an embodiment of the present disclosure includes: a first substrate including a first junction portion; and a second substrate including a second junction portion. The second junction portion is joined to the first junction portion. The first substrate further includes a first multilayer wiring layer in which one surface of a first wiring line faces a first insulating layer and another surface opposed to the one surface is in contact with a second insulating layer. The first multilayer wiring layer is electrically coupled to the first junction portion via the first insulating layer. The first wiring line is formed closest to a junction surface with the second substrate. The second insulating layer has a lower relative dielectric constant than a relative dielectric constant of the first insulating layer.Type: GrantFiled: June 11, 2019Date of Patent: September 5, 2023Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Hiroyuki Kawashima, Ryoichi Nakamura, Yoshihisa Kagawa, Yuusaku Kobayashi
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Patent number: 11626356Abstract: A first semiconductor device includes a first substrate including a first electrode and a second electrode at a first surface side of the first substrate opposite to a light incident surface side of the first substrate; and a second substrate including a photodiode, a transfer transistor, and a third electrode and a fourth electrode at a first surface side of the second substrate facing the first surface of the first substrate, and a plurality of transistors.Type: GrantFiled: February 18, 2022Date of Patent: April 11, 2023Assignee: SONY GROUP CORPORATIONInventors: Nobutoshi Fujii, Yoshihisa Kagawa
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Publication number: 20230098931Abstract: A first semiconductor device includes: a first wiring layer including a first interlayer insulating film, a first electrode pad, and a first dummy electrode, the first electrode pad being embedded in the first interlayer insulating film and having one surface located on same plane as one surface of the first interlayer insulating film, and the first dummy electrode being embedded in the first interlayer insulating film, having one surface located on same plane as the one surface of the first interlayer insulating film, and being disposed around the first electrode pad; and a second wiring layer including a second interlayer insulating film, a second electrode pad, and a second dummy electrode, the second electrode pad being embedded in the second interlayer insulating film, having one surface located on same surface as one surface of the second interlayer insulating film, and being bonded to the first electrode pad, and the second dummy electrode having one surface located on same plane as the surface locatedType: ApplicationFiled: December 7, 2022Publication date: March 30, 2023Applicant: Sony Group CorporationInventors: Nobutoshi Fujii, Yoshihisa Kagawa
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Patent number: 11587857Abstract: A first semiconductor device includes: a first wiring layer including a first interlayer insulating film, a first electrode pad, and a first dummy electrode, the first electrode pad being embedded in the first interlayer insulating film and having one surface located on same plane as one surface of the first interlayer insulating film, and the first dummy electrode being embedded in the first interlayer insulating film, having one surface located on same plane as the one surface of the first interlayer insulating film, and being disposed around the first electrode pad; and a second wiring layer including a second interlayer insulating film, a second electrode pad, and a second dummy electrode, the second electrode pad being embedded in the second interlayer insulating film, having one surface located on same surface as one surface of the second interlayer insulating film, and being bonded to the first electrode pad, and the second dummy electrode having one surface located on same plane as the surface locatedType: GrantFiled: April 4, 2018Date of Patent: February 21, 2023Assignee: SONY CORPORATIONInventors: Nobutoshi Fujii, Yoshihisa Kagawa
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Patent number: 11569123Abstract: Disclosed herein is a semiconductor device, including: a first substrate including a first electrode, and a first insulating film configured from a diffusion preventing material for the first electrode and covering a periphery of the first electrode, the first electrode and the first insulating film cooperating with each other to configure a bonding face; and a second substrate bonded to and provided on the first substrate and including a second electrode joined to the first electrode, and a second insulating film configured from a diffusion preventing material for the second electrode and covering a periphery of the second electrode, the second electrode and the second insulating film cooperating with each other to configure a bonding face to the first substrate.Type: GrantFiled: March 8, 2021Date of Patent: January 31, 2023Assignee: SONY CORPORATIONInventors: Yoshihisa Kagawa, Kenichi Aoyagi, Yoshiya Hagimoto, Nobutoshi Fujii
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Publication number: 20220279534Abstract: A wireless communication device includes a transmission processing unit communicable with each of multiple communication peer devices through switching between beam directions in a time division manner, and a control unit that allows beam information representing how beams are used by the multiple communication peer devices with which the transmission processing unit is communicable to be shared by the multiple communication peer devices.Type: ApplicationFiled: May 16, 2022Publication date: September 1, 2022Applicant: Mitsubishi Electric CorporationInventors: Fumihiro HASEGAWA, Shigenori TANI, Nobuyoshi HORIE, Hiroyasu SANO, Yoshihisa KAGAWA
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Publication number: 20220246498Abstract: A first semiconductor device includes: a first wiring layer including a first interlayer insulating film, a first electrode pad, and a first dummy electrode, the first electrode pad being embedded in the first interlayer insulating film and having one surface located on same plane as one surface of the first interlayer insulating film, and the first dummy electrode being embedded in the first interlayer insulating film, having one surface located on same plane as the one surface of the first interlayer insulating film, and being disposed around the first electrode pad; and a second wiring layer including a second interlayer insulating film, a second electrode pad, and a second dummy electrode, the second electrode pad being embedded in the second interlayer insulating film, having one surface located on same surface as one surface of the second interlayer insulating film, and being bonded to the first electrode pad, and the second dummy electrode having one surface located on same plane as the surface locatedType: ApplicationFiled: February 18, 2022Publication date: August 4, 2022Applicant: Sony Group CorporationInventors: Nobutoshi Fujii, Yoshihisa Kagawa
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Publication number: 20210366958Abstract: A semiconductor device includes a first substrate having an attaching surface on which first electrodes and a first insulating film are exposed, an insulating thin film that covers the attaching surface of the first substrate, and a second substrate which has an attaching surface on which second electrodes and a second insulating film are exposed and is attached to the first substrate in a state in which the attaching surface of the second substrate and the attaching surface of the first substrate are attached together sandwiching the insulating thin film therebetween, and the first electrodes and the second electrodes deform and break a part of the insulating thin film so as to be directly electrically connected to each other.Type: ApplicationFiled: August 3, 2021Publication date: November 25, 2021Applicant: Sony Group CorporationInventors: Nobutoshi Fujii, Yoshiya Hagimoto, Kenichi Aoyagi, Yoshihisa Kagawa
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Patent number: 11107855Abstract: A semiconductor device includes a first substrate having an attaching surface on which first electrodes and a first insulating film are exposed, an insulating thin film that covers the attaching surface of the first substrate, and a second substrate which has an attaching surface on which second electrodes and a second insulating film are exposed and is attached to the first substrate in a state in which the attaching surface of the second substrate and the attaching surface of the first substrate are attached together sandwiching the insulating thin film therebetween, and the first electrodes and the second electrodes deform and break a part of the insulating thin film so as to be directly electrically connected to each other.Type: GrantFiled: August 28, 2019Date of Patent: August 31, 2021Assignee: SONY CORPORATIONInventors: Nobutoshi Fujii, Yoshiya Hagimoto, Kenichi Aoyagi, Yoshihisa Kagawa
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Publication number: 20210265200Abstract: Disclosed herein is a semiconductor device, including: a first substrate including a first electrode, and a first insulating film configured from a diffusion preventing material for the first electrode and covering a periphery of the first electrode, the first electrode and the first insulating film cooperating with each other to configure a bonding face; and a second substrate bonded to and provided on the first substrate and including a second electrode joined to the first electrode, and a second insulating film configured from a diffusion preventing material for the second electrode and covering a periphery of the second electrode, the second electrode and the second insulating film cooperating with each other to configure a bonding face to the first substrate.Type: ApplicationFiled: March 8, 2021Publication date: August 26, 2021Applicant: Sony CorporationInventors: Yoshihisa Kagawa, Kenichi Aoyagi, Yoshiya Hagimoto, Nobutoshi Fujii
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Publication number: 20210233946Abstract: The present technology relates to a semiconductor device, a solid-state image pickup element, an imaging device, and an electronic apparatus that can suppress characteristic fluctuations caused by capacitance fluctuations due to a dummy wire, while maintaining an affixing bonding strength by the dummy wire. Two or more chips in which wires that are electrically connected are formed on bonding surfaces and the bonding surfaces opposing each other are bonded to be laminated are included and, with respect to a region where the wires are periodically and repeatedly disposed in sharing units each made up of a plurality of pixels sharing the same floating diffusion contact, a dummy wire is disposed at the center position thereof on the bonding surface at a pitch of the sharing unit. The present technology can be applied to a CMOS image sensor.Type: ApplicationFiled: April 13, 2021Publication date: July 29, 2021Applicant: SONY GROUP CORPORATIONInventors: Rena SUZUKI, Takeshi MATSUNUMA, Naoki JYO, Yoshihisa KAGAWA
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Publication number: 20210183778Abstract: A semiconductor device according to an embodiment of the present disclosure includes: a first substrate including a first junction portion; and a second substrate including a second junction portion. The second junction portion is joined to the first junction portion. The first substrate further includes a first multilayer wiring layer in which one surface of a first wiring line faces a first insulating layer and another surface opposed to the one surface is in contact with a second insulating layer. The first multilayer wiring layer is electrically coupled to the first junction portion via the first insulating layer. The first wiring line is formed closest to a junction surface with the second substrate. The second insulating layer has a lower relative dielectric constant than a relative dielectric constant of the first insulating layer.Type: ApplicationFiled: June 11, 2019Publication date: June 17, 2021Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Hiroyuki KAWASHIMA, Ryoichi NAKAMURA, Yoshihisa KAGAWA, Yuusaku KOBAYASHI
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Patent number: 11004879Abstract: The present technology relates to a semiconductor device, a solid-state image pickup element, an imaging device, and an electronic apparatus that can suppress characteristic fluctuations caused by capacitance fluctuations due to a dummy wire, while maintaining an affixing bonding strength by the dummy wire. Two or more chips in which wires that are electrically connected are formed on bonding surfaces and the bonding surfaces opposing each other are bonded to be laminated are included and, with respect to a region where the wires are periodically and repeatedly disposed in sharing units each made up of a plurality of pixels sharing the same floating diffusion contact, a dummy wire is disposed at the center position thereof on the bonding surface at a pitch of the sharing unit. The present technology can be applied to a CMOS image sensor.Type: GrantFiled: February 19, 2020Date of Patent: May 11, 2021Assignee: SONY CORPORATIONInventors: Rena Suzuki, Takeshi Matsunuma, Naoki Jyo, Yoshihisa Kagawa
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Patent number: 10985102Abstract: Disclosed herein is a semiconductor device, including: a first substrate including a first electrode, and a first insulating film configured from a diffusion preventing material for the first electrode and covering a periphery of the first electrode, the first electrode and the first insulating film cooperating with each other to configure a bonding face; and a second substrate bonded to and provided on the first substrate and including a second electrode joined to the first electrode, and a second insulating film configured from a diffusion preventing material for the second electrode and covering a periphery of the second electrode, the second electrode and the second insulating film cooperating with each other to configure a bonding face to the first substrate.Type: GrantFiled: May 13, 2019Date of Patent: April 20, 2021Assignee: Sony CorporationInventors: Yoshihisa Kagawa, Kenichi Aoyagi, Yoshiya Hagimoto, Nobutoshi Fujii
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Patent number: 10930845Abstract: A memory device includes: a memory layer that is isolated for each memory cell and stores information by a variation of a resistance value; an ion source layer that is formed to be isolated for each memory cell and to be laminated on the memory layer, and contains at least one kind of element selected from Cu, Ag, Zn, Al and Zr and at least one kind of element selected from Te, S and Se; an insulation layer that isolates the memory layer and the ion source layer for each memory cell; and a diffusion preventing barrier that is provided at a periphery of the memory layer and the ion source layer of each memory cell to prevent the diffusion of the element.Type: GrantFiled: April 18, 2019Date of Patent: February 23, 2021Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventor: Yoshihisa Kagawa
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Patent number: 10837448Abstract: A counter-rotating axial flow fan includes a first fan including a first impeller including first blades radially arranged around a predetermined central axis, a first motor rotating the first impeller around the central axis, and a first case surrounding an outer periphery of the first impeller, and a second fan including a second impeller including second blades radially arranged around the central axis, a second motor rotating the second impeller around the central axis, and a second case surrounding an outer periphery of the second impeller. End surfaces of the first and second cases contact each other at a first position in an axial direction, the first and second motors face in opposite directions from each other in the axial direction, and end surfaces of the first and second motors are opposite to each other at a second position that differs from the first position.Type: GrantFiled: March 15, 2019Date of Patent: November 17, 2020Assignee: NIDEC SERVO CORPORATIONInventors: Yoshihiko Kato, Takahiro Bamba, Yoshihisa Kagawa, Takanori Abe
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Patent number: 10804313Abstract: The present technology relates to a semiconductor device and a solid-state imaging device of which crack resistance can be improved in a simpler way. The semiconductor device has an upper substrate that is constituted by a Si substrate and wiring layers laminated on the Si substrate and a second substrate that is constituted by a Si substrate and wiring layers laminated on the Si substrate and is joined to the upper substrate. In addition, a pad for wire bonding or probing is formed in the upper substrate, and pads for protecting corner or side parts of the pad for wire bonding or probing are radially laminated and provided in each of the wiring layers between the pad and the Si substrate of the lower substrate. The present technology can be applied to a solid-state imaging device.Type: GrantFiled: June 6, 2018Date of Patent: October 13, 2020Assignee: Sony CorporationInventors: Yoshihisa Kagawa, Nobutoshi Fujii, Masanaga Fukasawa, Tokihisa Kaneguchi, Yoshiya Hagimoto, Kenichi Aoyagi, Ikue Mitsuhashi