Patents by Inventor Yoshihisa Kojima

Yoshihisa Kojima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200326862
    Abstract: According to one embodiment, a memory system includes a non-volatile memory and a controller. The memory includes a memory cell array. The controller is configured to control a transfer phase in which a command, an address, and first data are transferred to the memory, and a program phase in which the first data is programmed into the memory cell array by the memory after the transfer phase. The controller is configured to suspend the transfer phase after initiating the transfer phase before completion of the transfer phase, then read second data from the memory, and resume the transfer phase after reading of the second data is completed.
    Type: Application
    Filed: June 26, 2020
    Publication date: October 15, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Shizuka ENDO, Riki SUZUKI, Yoshihisa KOJIMA
  • Patent number: 10803953
    Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes: first memory cells, first word lines, a first row decoder, and a driver circuit. The first row decoder includes first transistors capable of coupling the first word lines to first signal lines, and a first block decoder supplying a first block selection signal to the first transistors. When the controller issues a data read command, the first block decoder asserts the first block selection signal to allow the first transistors to transfer a first voltage to a selected first word line, and a second voltage to unselected other first word lines. After data is read, the first block decoder continues asserting the first block selection signal, and the driver circuit transfers a third voltage.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: October 13, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Masanobu Shirakawa, Marie Takada, Tsukasa Tokutomi, Yoshihisa Kojima, Kiichi Tachi
  • Patent number: 10803930
    Abstract: According to one embodiment, a memory system comprising includes a semiconductor memory and a memory controller. The memory controller is configured to obtain first data read from the semiconductor memory using a first voltage, obtain second data read from the semiconductor memory using a second voltage, calculate a first value for a first section of the first data using the first data and the second data, calculate a second value for a second section of the first data using the first data and the second data, calculate a third value for a third section of the first data using the first data and the second data, and correct an error of the first data using the first to third values.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: October 13, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Masahiro Kiyooka, Yoshihisa Kojima, Toshikatsu Hida
  • Patent number: 10796776
    Abstract: According to one embodiment, a nonvolatile memory includes: a memory cell array including memory cells; and a controller configured to execute a first refresh process on receiving a first command. The first refresh process includes reprogramming at least one second memory cell among first memory cells to which data has been programmed in a first group. In executing the first refresh process, the controller is configured to: select the second memory cell by verifying with a first voltage using a first amount in a case where the second memory cell has been programmed using the first voltage; and select the second memory cell by verifying with a second voltage using a second amount in a case where the second memory cell has been programmed using the second voltage.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: October 6, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Riki Suzuki, Masanobu Shirakawa, Yoshihisa Kojima, Marie Takada, Tsukasa Tokutomi
  • Publication number: 20200303018
    Abstract: A memory system includes a nonvolatile memory and a controller. The nonvolatile memory includes memory cells at intersection locations of stacked word lines and a memory pillar passing through the word lines in a stacking direction, the word lines including a first group of word lines stacked above a second group of word lines. The controller reads data of a first memory cell in a first read mode and reads data of a second memory cell in a second read mode. The first memory cell is, and the second memory cell is not, at an intersection location of a word line that is in a boundary area of the first and second groups of word lines and the memory pillar. The boundary area is adjacent to a location of the memory pillar where a width of the memory pillar discontinuously changes along the stacking direction.
    Type: Application
    Filed: December 26, 2019
    Publication date: September 24, 2020
    Inventors: Kazutaka TAKIZAWA, Yoshihisa KOJIMA, Masaaki NIIJIMA
  • Publication number: 20200301611
    Abstract: A memory system includes a non-volatile memory chip that includes a memory cell array, and a memory controller. The memory controller is configured to perform a read operation on the non-volatile memory chip by instructing the non-volatile memory chip to perform a sensing operation to read data stored in the memory cell array, estimating a time when the read data becomes ready to be transferred from the non-volatile memory chip to the memory controller, and instructing the non-volatile memory chip, after the estimated time, to perform a transfer operation to transfer the read data to the memory controller.
    Type: Application
    Filed: August 30, 2019
    Publication date: September 24, 2020
    Inventors: Marie SIA, Yoshihisa KOJIMA, Suguru NISHIKAWA, Riki SUZUKI
  • Publication number: 20200303012
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller that controls operation of the nonvolatile memory. The nonvolatile memory is configured to receive, from the memory controller, a first command for execution of at least one of an erase operation and a program operation; in response to receiving a second command from the memory controller during execution of a first operation requested by the first command, execute a second operation for suspending the first operation before the first operation reaches a given section; and in response to receiving a third command from the memory controller during the execution of the first operation, suspend the first operation after the given section.
    Type: Application
    Filed: February 25, 2020
    Publication date: September 24, 2020
    Applicant: Kioxia Corporation
    Inventors: Suguru NISHIKAWA, Riki SUZUKI, Yoshihisa KOJIMA
  • Publication number: 20200294605
    Abstract: A semiconductor memory device includes a memory cell array, an input/output circuit configured to output read data from the semiconductor memory device, a first data latch configured to latch data read from the memory cell array as the read data, a second data latch to which the read data is transferred from the first data latch and from which the read data is transferred to the input/output circuit, a signaling circuit configured to output a ready signal or a busy signal, and a control circuit configured to control the signaling circuit to output the busy signal while the read data is being latched in the first data latch during a read operation performed on the memory cell array and to output the ready signal while the read data latched in the first data latch is being transferred from the first latch to the second latch.
    Type: Application
    Filed: May 28, 2020
    Publication date: September 17, 2020
    Inventors: Takaya HANDA, Yoshihisa KOJIMA, Kiyotaka IWASAKI
  • Publication number: 20200293228
    Abstract: According to one embodiment, there is provided a memory system including a non-volatile memory, and a controller. The controller selects one read method from a plurality of read methods with different time required to perform a read operation on the non-volatile memory and issues a first read command according to the selected one read method to the non-volatile memory.
    Type: Application
    Filed: January 24, 2020
    Publication date: September 17, 2020
    Applicant: Kioxia Corporation
    Inventors: Takehiko AMAKI, Yoshihisa KOJIMA
  • Patent number: 10768679
    Abstract: In a memory system in an embodiment, in a case of normal operation, a control unit returns a write completion response upon completion of reception of write data from a host, and writes the write data into nonvolatile memory in a multiple values. In a case of unordinary power-off, changeover to operation using a backup battery is conducted and the control unit writes dirty data that is not completed in writing into the nonvolatile memory, into the nonvolatile memory with two values. When next boot, the control unit reads the dirty data from the nonvolatile memory into the volatile memory, and thereafter writes the dirty data into the nonvolatile memory in a multiple values.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: September 8, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Yoshihisa Kojima, Katsuhiko Ueki
  • Patent number: 10754553
    Abstract: According to one embodiment, a memory system includes a non-volatile memory and a controller. The memory includes a memory cell array. The controller is configured to control a transfer phase in which a command, an address, and first data are transferred to the memory, and a program phase in which the first data is programmed into the memory cell array by the memory after the transfer phase. The controller is configured to suspend the transfer phase after initiating the transfer phase before completion of the transfer phase, then read second data from the memory, and resume the transfer phase after reading of the second data is completed.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: August 25, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Shizuka Endo, Riki Suzuki, Yoshihisa Kojima
  • Patent number: 10754560
    Abstract: A storage device includes a nonvolatile semiconductor memory and a controller. The controller is configured to predict power consumption that is required to carry out operations in accordance with access pattern and throughput received from a host, notify the predicted power consumption to the host, determine operating resources of at least one of the nonvolatile semiconductor memory and the controller to carry out the operations, on the basis of the permissible power consumption received from the host, and carry out the operations using the determined operating resources.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: August 25, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Motohiro Matsuyama, Yoshihisa Kojima
  • Patent number: 10747444
    Abstract: A semiconductor storage device comprises a nonvolatile semiconductor memory with memory regions, threads, and a controller. Each thread includes a buffer region in which write data from a host are stored before the write data are written to one of the memory regions, and the buffer region of each thread is different from buffer regions of the other threads. The controller receives stream data from the host, each stream data being associated with one of multiple stream identifications, allocates each stream identification to one of the threads according to priority levels assigned to the stream identifications, such that a stream identification assigned a highest priority level is allocated to a thread to which none of other stream identifications are allocated, and writes each stream data stored in the buffer regions to one of the memory regions according to stream identification of the stream data.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: August 18, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Motohiro Matsuyama, Yoshihisa Kojima
  • Patent number: 10747449
    Abstract: According to one embodiment, a memory system is provided with a nonvolatile memory, a controller, a volatile memory and an address translation table. The address translation table includes a high level and a plurality of low levels. The high level indicates positions in the nonvolatile memory in which the low levels are recorded. The low levels indicate positions in the nonvolatile memory in which data is recorded. The controller holds the high level of the address translation table in the first area of the volatile memory, and shuts off the supply of power to the second area of the volatile memory based on a transition from a normal-power state to a low-power state.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: August 18, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Tatsuya Zettsu, Katsuhiko Ueki, Yoshihisa Kojima, Hiroshi Yao, Kenichiro Yoshii, Ikuo Magaki
  • Patent number: 10740101
    Abstract: According to one embodiment, a memory system includes a first nonvolatile memory, and a controller. The controller executes, to the first memory, a program operation first and a first read operation next. The program operation is an operation including (i) acquiring a first temperature, (ii) storing the first temperature, and (iii) controlling the access circuit to set a threshold voltage of a memory cell transistor at a value corresponding to first data. The first read operation is an operation for (i) acquiring a second temperature, (ii) computing a difference between the second and the first temperature, (iii) acquiring a first determination voltage, (iv) correcting the first determination voltage according to the difference, and (v) controlling the first memory to acquire second data corresponding to the threshold voltage on the basis of a comparison between the threshold voltage of the memory cell transistor and the corrected first determination voltage.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: August 11, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Kazutaka Takizawa, Yoshihisa Kojima, Masaaki Niijima
  • Patent number: 10719396
    Abstract: A controller executes a plurality of first read operations and, when receiving a read request from a host, executes a second read operation. The first read operations are executed using, as determination voltage, different candidate values among a plurality of candidate values. In each of the first read operations, the controller executes error correction to acquired data, and acquires a first candidate value on the basis of results of the error corrections in the first read operations. The second read operation is executed using, as the determination voltage, a second candidate value that is ranked higher than the first candidate value.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: July 21, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Shohei Asami, Yoshihisa Kojima
  • Publication number: 20200226022
    Abstract: A memory system includes a nonvolatile memory, a memory controller included in a first package, and a memory interface circuit included in a second package that is different from the first package. The memory controller includes an encoder for performing encoding for error correction. The memory controller is configured to encode first data into second data using the encoder, and program the second data into a location in the nonvolatile memory. The memory interface circuit is interposed between the memory and the memory controller. The memory interface circuit includes a decoder for performing decoding for error correction. The memory interface circuit is configured to read third data from a first location in the nonvolatile memory, diagnose the third data by decoding the third data using the decoder, and convey a result of the diagnosis to the memory controller.
    Type: Application
    Filed: March 30, 2020
    Publication date: July 16, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Takashi IDE, Yoshihisa KOJIMA
  • Patent number: 10706940
    Abstract: A semiconductor memory device includes a memory cell array, an input/output circuit configured to output read data from the semiconductor memory device, a first data latch configured to latch data read from the memory cell array as the read data, a second data latch to which the read data is transferred from the first data latch and from which the read data is transferred to the input/output circuit, a signaling circuit configured to output a ready signal or a busy signal, and a control circuit configured to control the signaling circuit to output the busy signal while the read data is being latched in the first data latch during a read operation performed on the memory cell array and to output the ready signal while the read data latched in the first data latch is being transferred from the first latch to the second latch.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: July 7, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takaya Handa, Yoshihisa Kojima, Kiyotaka Iwasaki
  • Patent number: 10697659
    Abstract: An air-conditioning control system includes a plurality of air-conditioning apparatuses each provided with an indoor unit and an outdoor unit; a master remote control device associated with one or more of the plurality of air-conditioning apparatuses and adapted to control operation of the associated air-conditioning apparatus or apparatuses; and one or more slave remote control devices connected with the master remote control device using a first communication system, associated with a remaining one or ones of the plurality of air-conditioning apparatuses, and adapted to control operation of the associated air-conditioning apparatus or apparatuses, in which the indoor units of the air-conditioning apparatuses are connected with an associated one or ones of the master remote control device and the slave remote control device or devices using a second communication system different from the first communication system, and the master remote control device controls the operation of the remaining air-conditioning
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: June 30, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yoshiaki Koizumi, Yoshihisa Kojima, Mitsuru Kitazaki, Hidetoshi Muramatsu
  • Patent number: 10684795
    Abstract: A storage device includes a nonvolatile semiconductor memory and a controller. The nonvolatile semiconductor memory includes a first region and a second region. The controller classifies a plurality of read requests for reading data from the nonvolatile semiconductor memory into first read requests for reading data from the first region and second read requests for reading data from the second region, pairs one of the first read requests with one of the second read requests to generate a third read request, and outputs the third read request to the nonvolatile semiconductor memory.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: June 16, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Yoshihisa Kojima