Abstract: A semiconductor device may include an n-MOS transistor, and a p-MOS transistor. The p-MOS transistor may include, but is not limited to, a gate insulating film and a gate electrode. The gate electrode may have an adjacent portion that is adjacent to the gate insulating film. The adjacent portion may include a polysilicon that contains an n-type dopant and a p-type dopant.

Abstract: A method for manufacturing a semiconductor device according to the present invention includes the steps of providing a semiconductor substrate in which an element isolation region and active regions surrounded by the element isolation region are formed, forming a plurality of conductive lines disposed such that the conductive lines cross the active regions, forming an insulating film over the entire surface including the conductive lines, and etching away the insulating film situated over the active regions between the conductive lines so as to form contact holes. After an anti-etching film is formed to protect the surfaces in the contact holes, wet etching is conducted to remove the insulating film in the contact holes so as to form the contact holes.

Abstract: An antifuse element includes a plurality of MOS transistors; a first electrode to which source electrodes of the plurality of MOS transistors are commonly connected; a second electrode to which gate electrodes of the plurality of MOS transistors are commonly connected; a third electrode to which at least one of drain electrodes of the plurality of MOS transistors is capable of being connected; and an insulation film provided between the drain electrodes of the plurality of MOS transistors and the third electrode, wherein the insulation on at least one position in said insulation film and that corresponds to one of the drain electrodes is broken down.

Abstract: A semiconductor device includes a semiconductor substrate, an isolation region including an insulator in a trench formed in the semiconductor substrate, an active region including a semiconductor region surrounded by the insulator in the trench and a single-crystal silicon layer formed on the semiconductor region, a gate insulating film formed on the single-crystal silicon layer, a gate electrode provided on the gate insulating film so as to stride across the active region, and diffusion layers provided in the active region on opposite sides of the gate electrode.

Abstract: A semiconductor device may include an n-MOS transistor, and a p-MOS transistor. The p-MOS transistor may include, but is not limited to, a gate insulating film and a gate electrode. The gate electrode may have an adjacent portion that is adjacent to the gate insulating film. The adjacent portion may include a polysilicon that contains an n-type dopant and a p-type dopant.

Abstract: This semiconductor device includes a trench gate transistor including a groove formed on a semiconductor, a gate electrode formed in the groove via a gate insulating film, and a source and a drain disposed near the gate electrode on the semiconductor substrate via the gate insulating film. The gate electrode extends from an inner side of the groove to an outer side of the groove. The gate electrode has a misalignment portion in a width direction from the inner side of the groove to the outer side of the groove. The misalignment portion of the gate electrode is formed at a side higher than an opening edge of the groove. A height from the opening edge of the groove to the misalignment portion is larger than a thickness of the gate insulating film.

Abstract: An antifuse includes a first conductor pattern, a sidewall insulating film formed on a side of the first conductor pattern, and a second conductor pattern formed so that the sidewall insulating film is interposed between the first and second conductor patterns and so as to face the side of the first conductor pattern. The antifuse utilizes the sidewall insulating film as a capacitor insulating film of a capacitor.

Abstract: A method for manufacturing a semiconductor device having a P-type MOSFET and an N-type MOSFET, the method comprising the steps of: forming a gate insulating film, a non-doped polysilicon film, a metal silicide film, a metal nitride film and a metal film on a semiconductor substrate; processing at least the metal film, the metal nitride film and the metal silicide film to pattern them into the shape of a gate such that the portion of the meal silicide film that forms part of a gate electrode of a P-type MOSFET and the portion of the meal silicide film that forms part of a gate electrode of an N-type MOSFET are separated from each other; introducing P-type and N-type impurities into the respective regions of the non-doped polysilicon film where the P-type and N-type MOSFETs are formed; performing thermal treatment to diffuse the impurities; and patterning the polysilicon film with the impurities introduced into the shape of the gate.

Abstract: A method for manufacturing a semiconductor device according to the present invention includes the steps of providing a semiconductor substrate in which an element isolation region and active regions surrounded by the element isolation region are formed, forming a plurality of conductive lines disposed such that the conductive lines cross the active regions, forming an insulating film over the entire surface including the conductive lines, and etching away the insulating film situated over the active regions between the conductive lines so as to form contact holes. After an anti-etching film is formed to protect the surfaces in the contact holes, wet etching is conducted to remove the insulating film in the contact holes so as to form the contact holes.

Abstract: A method for manufacturing a semiconductor device having a P-type MOSFET and an N-type MOSFET, the method comprising the steps of: forming a gate insulating film, a non-doped polysilicon film, a metal silicide film, a metal nitride film and a metal film on a semiconductor substrate; processing at least the metal film, the metal nitride film and the metal silicide film to pattern them into the shape of a gate such that the portion of the meal silicide film that forms part of a gate electrode of a P-type MOSFET and the portion of the meal silicide film that forms part of a gate electrode of an N-type MOSFET are separated from each other; introducing P-type and N-type impurities into the respective regions of the non-doped polysilicon film where the P-type and N-type MOSFETs are formed; performing thermal treatment to diffuse the impurities; and patterning the polysilicon film with the impurities introduced into the shape of the gate.

Abstract: A biodegradable resin composition including a saponified ethylene-vinyl acetate copolymer and a starch-based macromolecular substance. The saponified ethylene-vinyl acetate copolymer is one having an ethylene content of 20 to 60 mole %, a vinyl acetate saponification degree of not less than 90 mole %, a melt flow index of 1 to 100 g/10 min as measured under a load of 2160 g at 210.degree. C., and a melt viscosity ratio .eta..sub.60 /.eta..sub.5 of 0.5 to 4 where .eta..sub.60 means the melt viscosity after 60 minutes of standing at 250.degree. C. and the .eta..sub.5 means the melt viscosity after 5 minutes of standing at 250.degree. C. and a starch-based macromolecular substance. A layer of the above composition can be used to fabricate a laminate with a substrate material of a different kind, such as a photodegradable polymer.