Patents by Inventor Yoshiki Matsuda

Yoshiki Matsuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5533141
    Abstract: A portable pen pointing device and a processing system with pen pointing device which can be easily used. The portable pen pointing device includes a memory for storing user's specific penmanship/handwriting information and a pen interface unit for supplying the user's specific penmanship/handwriting information to a processor body of the processing system. The processor body interprets a writing sample on the basis of the user's specific penmanship/handwriting information supplied from the portable pen pointing device through the pen interface unit thereof. With this construction, there is no need to read information from a storage medium such as a flexible disk in which a user's specific dictionary for penmanship/handwriting interpretation is written. Also, an operation of establishing a certain writing environment becomes unnecessary or easy.
    Type: Grant
    Filed: December 23, 1992
    Date of Patent: July 2, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Seiji Futatsugi, Keiji Kojima, Yoshiki Matsuda, Yoshinori Kitahara, Masato Mogaki
  • Patent number: 5426752
    Abstract: A method for allocating real pages larger than a conventional size to a plurality of virtual pages of the conventional size in a system including a real storage containing a plurality of real pages and a storage key for holding storage keys used for storage protection purposes of the real pages. The method includes the steps of (A) allocating one of plural split regions having the conventional size obtained by subdividing one of a plurality of real pages having a larger size equal to a value n being a positive integer larger than 1) times larger than the conventional size, to one virtual page having the conventional size (B) repeating step (A) so that split regions having the conventional size within the one real page and within other real pages having the larger size are allocated to virtual pages having the conventional size.
    Type: Grant
    Filed: April 25, 1994
    Date of Patent: June 20, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Kikuo Takahasi, Toyohiko Kagimasa, Yoshiki Matsuda, Toshiaki Mori
  • Patent number: 5398313
    Abstract: A program is written using actual data as arguments of commands that are executed with the data when the commands are entered in the program to produce results that are compared with the desired results of the program. When the results are successful, they constitute a first sequence of the program. When execution of the first sequence of the program is unsuccessful with respect to other specific data, automatic prompting results in entry of new commands that are automatically executed with respect to the new data, without reentry of the new data and without reexecution of the first sequence to provide a second sequence with successful execution. Therefore, the program will be constituted by two or more sequences with conditional branching between the sequences as to the success of each sequence in producing the desired results with the data then being operated upon. The program preferably includes an application program that controls a computer system for the writing and branching.
    Type: Grant
    Filed: April 4, 1991
    Date of Patent: March 14, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Keiji Kojima, Yoshiki Matsuda
  • Patent number: 4868740
    Abstract: A data processor which specifies either of a predetermined maximum length of an adddress (a bits) and a length of an address less than the former length and at plural registers having a number of length of bits (r bits) of the maximum address length or greater. The data processor reads out lower-order d bits for data or r bits for an address of the one of the plural registers (7) specified by a first instruction to perform an arithmetic or logic operation, and writes the result into one of the plural registers. Moreover, the processor reads out bits having specified length of an address from the one of the plural registers specified in a second instruction to generate an a-bit address, and reads out d for data or r bits for an address from a main storage device (5) in response to the thus-generated address to write the d or r bits into one of the plural registers.
    Type: Grant
    Filed: June 3, 1987
    Date of Patent: September 19, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Toyohiko Kagimasa, Yoshiki Matsuda, Kikuo Takahashi, Seiichi Yoshizumi